PATTGEN Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	17.000s	271.782us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	14.799us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	6.000s	17.858us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	188.468us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	63.714us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	225.346us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	6.000s	17.858us	20	20	100.00
		pattgen_csr_aliasing	3.000s	63.714us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.650m	8.219ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.717m	9.174ms	50	50	100.00
V2	error	pattgen_error	7.000s	91.781us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.917m	5.356ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	37.819us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	12.989us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	80.760us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	80.760us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	14.799us	5	5	100.00
		pattgen_csr_rw	6.000s	17.858us	20	20	100.00
		pattgen_csr_aliasing	3.000s	63.714us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	22.960us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	14.799us	5	5	100.00
		pattgen_csr_rw	6.000s	17.858us	20	20	100.00
		pattgen_csr_aliasing	3.000s	63.714us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	22.960us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	127.790us	20	20	100.00
		pattgen_sec_cm	7.000s	36.173us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	127.790us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	37.000m	110.451ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	5.467m	10.012ms	47	50	94.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:

Test pattgen_stress_all_with_rand_reset has 32 failures.

0.pattgen_stress_all_with_rand_reset.69143462743011369729202528734435508010620082415140669718556114087754329746267
Line 792, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 36494464918 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 36494471838 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 36494471838 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 36494513506 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.86871583467726414124989731924280739120401874565136345097684038936320612732164
Line 1251, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 97140307621 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 97140315419 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 97140315419 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 97140385187 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 30 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 19.pattgen_stress_all_with_rand_reset.80642677304162686936394507249918277678874021298008003699857612797666809121416
    Line 535, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 23403616545 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 29.pattgen_stress_all_with_rand_reset.56397353058304333580326299017661611720507686317095258262137134191141793510495
    Line 906, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 211105570751 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 1.pattgen_inactive_level.111574366945778926862396969481050742116181022992342753374212317451842060000835
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10035276386 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x184038d0, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10035276386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 3.pattgen_inactive_level.44758057905089612113894812671147209621688164250348879735577622650644240365839
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10012045882 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x29da3a10, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
  UVM_INFO @ 10012045882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 16.pattgen_inactive_level.46687472056762756207435795413290842208831116446969353337188034884008948744137
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10012230811 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xaa87fdd0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10012230811 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```