PATTGEN Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	144.491us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	25.284us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	43.610us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	286.713us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	30.776us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	24.898us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	43.610us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.776us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.800m	10.528ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	3.510ms	50	50	100.00
V2	error	pattgen_error	7.000s	109.710us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.683m	29.295ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	15.424us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	11.502us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	311.959us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	311.959us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	25.284us	5	5	100.00
		pattgen_csr_rw	7.000s	43.610us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.776us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	16.202us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	25.284us	5	5	100.00
		pattgen_csr_rw	7.000s	43.610us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.776us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	16.202us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	50.426us	20	20	100.00
		pattgen_sec_cm	12.000s	120.964us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	50.426us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	36.383m	99.041ms	13	50	26.00
V3		TOTAL			13	50	26.00
	Unmapped tests	pattgen_inactive_level	1.867m	10.026ms	48	50	96.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

0.pattgen_stress_all_with_rand_reset.72758613047834197845253504333763817292621950521213715830306447047875341806211
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 695466659 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 695526476 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 695526476 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 695993145 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.50422633634891874865869457671286310952443699385504906053695185071469022338962
Line 510, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16469197461 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 16469201509 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 16469201509 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 16469253594 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 10.pattgen_stress_all_with_rand_reset.67744902578602778775200429766085696675957365766826785261234217165415095507383
    Line 661, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/10.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 24285505648 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 20.pattgen_stress_all_with_rand_reset.54338420200234476450636806797071807579820886169667365951995671016473100899597
    Line 1085, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 409943480137 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 27.pattgen_inactive_level.48240528464901553388383366755533133868619691515308257818496432158975183738836
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10030418863 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x54071c90, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10030418863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 44.pattgen_inactive_level.29329118685036093661678884216247846682469908623993040097482684270963053556481
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10025561651 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xaf983a90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10025561651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```