PATTGEN Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	355.377us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	55.075us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	54.652us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	374.921us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	59.795us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	119.142us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	54.652us	20	20	100.00
		pattgen_csr_aliasing	3.000s	59.795us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.717m	8.218ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	2.714ms	50	50	100.00
V2	error	pattgen_error	3.000s	147.215us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.967m	2.765ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	18.262us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	15.705us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	109.752us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	109.752us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	55.075us	5	5	100.00
		pattgen_csr_rw	3.000s	54.652us	20	20	100.00
		pattgen_csr_aliasing	3.000s	59.795us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	17.668us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	55.075us	5	5	100.00
		pattgen_csr_rw	3.000s	54.652us	20	20	100.00
		pattgen_csr_aliasing	3.000s	59.795us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	17.668us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	81.711us	20	20	100.00
		pattgen_sec_cm	3.000s	69.505us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	81.711us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	29.800m	97.896ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	1.433m	10.013ms	48	50	96.00
		TOTAL			532	570	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

0.pattgen_stress_all_with_rand_reset.42170677998520423468907433872908939872765887468117991842238402563561733302947
Line 342, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13170605087 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 13170622130 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13170622130 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 13170811319 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.43166376908484756260027378290809790877837202231136224394018558101881303171302
Line 441, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35125811194 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 35125850985 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 35125850985 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 35126225988 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 21.pattgen_stress_all_with_rand_reset.71501878211642352938472131245023125673969004789895245126910488849415022830597
    Line 490, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 51388649742 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - 30.pattgen_stress_all_with_rand_reset.1939248292090447714881331388613555614245930833710092134652181198952769299700
    Line 314, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1541473962 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 29.pattgen_inactive_level.86764101151637655848316759692270885025709606081151095475825021284553565151701
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10361372599 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3ddda290, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
  UVM_INFO @ 10361372599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 45.pattgen_inactive_level.63069186531888077072417384415992466491872743469717148401648793639188163334803
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10012729633 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x331ef0d0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10012729633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```