PATTGEN Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	12.000s	266.959us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	8.000s	66.208us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	38.064us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	8.000s	192.473us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	121.475us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	28.899us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	38.064us	20	20	100.00
		pattgen_csr_aliasing	3.000s	121.475us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.667m	15.779ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	18.774ms	50	50	100.00
V2	error	pattgen_error	9.000s	60.101us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.833m	11.096ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	42.255us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	15.375us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	13.000s	37.797us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	13.000s	37.797us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	8.000s	66.208us	5	5	100.00
		pattgen_csr_rw	7.000s	38.064us	20	20	100.00
		pattgen_csr_aliasing	3.000s	121.475us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	51.244us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	8.000s	66.208us	5	5	100.00
		pattgen_csr_rw	7.000s	38.064us	20	20	100.00
		pattgen_csr_aliasing	3.000s	121.475us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	51.244us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	13.000s	153.750us	20	20	100.00
		pattgen_sec_cm	3.000s	39.442us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	13.000s	153.750us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	33.017m	104.295ms	19	50	38.00
V3		TOTAL			19	50	38.00
	Unmapped tests	pattgen_inactive_level	5.433m	10.010ms	47	50	94.00
		TOTAL			536	570	94.04

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

Test pattgen_stress_all_with_rand_reset has 27 failures.

4.pattgen_stress_all_with_rand_reset.13632031749627110437751504022555487553510012515083536569902016504231309647371
Line 488, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8218950353 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8218956711 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8218956711 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 8219050464 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

7.pattgen_stress_all_with_rand_reset.20741911548852516033172900897614419312669035265217074940306715750304693908361
Line 310, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 701939343 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 701946725 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 701946725 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 701987961 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 25 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 0.pattgen_stress_all_with_rand_reset.99595008626555694818723636461032738176503241223159190612282319269824652500801
    Line 1124, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 123612669028 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 42.pattgen_stress_all_with_rand_reset.47564011974104851666347936951614869812845812282807651109487726690680850065152
    Line 318, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 448136544 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 2.pattgen_inactive_level.92546281756159269251105063960750393372151364111896753601353996484160690031805
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010153895 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x39a02bd0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10010153895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 27.pattgen_inactive_level.61178845026621721986332034947924816325679999183969217198379794774021760092135
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10933379573 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x680a2110, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10933379573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 32.pattgen_inactive_level.102701408820903414007714174732871755752259977978163141567112871943390461656177
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10026115766 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8d8b23d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10026115766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```