PATTGEN Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	347.648us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	49.922us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	43.642us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.095ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	90.160us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	7.000s	160.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	43.642us	20	20	100.00
		pattgen_csr_aliasing	2.000s	90.160us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	6.031ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.767m	2.634ms	50	50	100.00
V2	error	pattgen_error	9.000s	34.159us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.250m	19.724ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	18.203us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	16.641us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	227.540us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	227.540us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	49.922us	5	5	100.00
		pattgen_csr_rw	2.000s	43.642us	20	20	100.00
		pattgen_csr_aliasing	2.000s	90.160us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	75.003us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	49.922us	5	5	100.00
		pattgen_csr_rw	2.000s	43.642us	20	20	100.00
		pattgen_csr_aliasing	2.000s	90.160us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	75.003us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	7.000s	140.221us	20	20	100.00
		pattgen_sec_cm	2.000s	239.204us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	7.000s	140.221us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	35.900m	113.759ms	10	50	20.00
V3		TOTAL			10	50	20.00
	Unmapped tests	pattgen_inactive_level	1.350m	10.018ms	44	50	88.00
		TOTAL			524	570	91.93

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:

Test pattgen_stress_all_with_rand_reset has 37 failures.

2.pattgen_stress_all_with_rand_reset.13936231750205711848600148790034068680256772098746319537584424167483401604206
Line 1320, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 149005468770 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 149005479662 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 149005479662 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 149005646326 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.4650504944005191374282602979975026449322360685696315022862572217494205861399
Line 503, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 50457500395 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 50457534239 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 50457534239 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 50457841931 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 35 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 0.pattgen_stress_all_with_rand_reset.42409237099684036329822975482639315333731728679219417041634135019865064411058
    Line 385, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4159087188 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 24.pattgen_stress_all_with_rand_reset.106379165638884233113840903537118948295244270286621889304404001404400785749612
    Line 449, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7816419280 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 3.pattgen_inactive_level.46534263917902632940517956501588652396476064136231252860233762016229080330432
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10086261257 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbcf9bf90, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10086261257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.pattgen_inactive_level.6804654826177792513504747322711024004795039795767767534978267541535118600870
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10462332757 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x303b4ad0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10462332757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=4) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 2.pattgen_inactive_level.75840311272080337422004177254111690562286878767500489002582365525621247013429
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008892409 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x158e0e50, Comparison=CompareOpEq, exp_data=0x0, call_count=4)
  UVM_INFO @ 10008892409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 32.pattgen_stress_all_with_rand_reset.59914325562775886509470291350984895199401660862381616927311870467722123171953
    Line 795, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 79089720650 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @11176
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 36.pattgen_inactive_level.79062215970521207590647388999135055288266571143425923813354056147574464385496
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015260847 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe893ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10015260847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 37.pattgen_inactive_level.37121215623300467650245034533363763246182211383723234953000623441576698239932
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10017942193 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x80906f90, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10017942193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 44.pattgen_inactive_level.85149612831868734057568692016781799758341907964084074928597677231604594335081
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006537658 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa6019550, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10006537658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```