PATTGEN Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	195.790us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	12.000s	46.457us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	38.339us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	9.000s	194.076us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	7.000s	15.657us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	12.000s	63.038us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	38.339us	20	20	100.00
		pattgen_csr_aliasing	7.000s	15.657us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.950m	3.949ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	7.307ms	50	50	100.00
V2	error	pattgen_error	13.000s	26.921us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.967m	4.048ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	38.570us	50	50	100.00
V2	intr_test	pattgen_intr_test	15.000s	19.744us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	14.000s	106.671us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	14.000s	106.671us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	12.000s	46.457us	5	5	100.00
		pattgen_csr_rw	12.000s	38.339us	20	20	100.00
		pattgen_csr_aliasing	7.000s	15.657us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	36.617us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	12.000s	46.457us	5	5	100.00
		pattgen_csr_rw	12.000s	38.339us	20	20	100.00
		pattgen_csr_aliasing	7.000s	15.657us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	36.617us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	17.000s	203.227us	20	20	100.00
		pattgen_sec_cm	12.000s	359.758us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	17.000s	203.227us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.050m	354.146ms	10	50	20.00
V3		TOTAL			10	50	20.00
	Unmapped tests	pattgen_inactive_level	1.550m	10.012ms	45	50	90.00
		TOTAL			525	570	92.11

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 37 failures:

Test pattgen_stress_all_with_rand_reset has 37 failures.

0.pattgen_stress_all_with_rand_reset.106901890073774502540944551434793471581092155812815334298109056210833646648
Line 294, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 622117192 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 622122902 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 622122902 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 622185404 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.54831911379981744115631895170917414023267903673906673244925912169545483752161
Line 1262, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 45015466612 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 45015468870 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 45015468870 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 8/10
  UVM_INFO @ 45015518870 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 35 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 1.pattgen_stress_all_with_rand_reset.99478442262415065552211946467608960787623603436179699436400372135741937022406
    Line 339, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 292725885 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 12.pattgen_stress_all_with_rand_reset.71060597274861341386227105263297216035562763689166971096414198706967106836752
    Line 650, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/12.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 84386741350 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 6.pattgen_inactive_level.18029611589317414639656017463427544313896794938829440550376476850217634312235
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10031868898 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4bd59810, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10031868898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 31.pattgen_inactive_level.6352914164040398071069572394156747618544036199027740024615825472935068552873
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10017366092 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8622f2d0, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10017366092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 21.pattgen_inactive_level.9714607354775352504377665717463322188182327234781985980252627482243679019798
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10039703082 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xecd8c990, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10039703082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 22.pattgen_inactive_level.56509445092847326618388555538252906039017052848241722881760370069874630867051
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10471104157 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x20e82a90, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10471104157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 45.pattgen_inactive_level.18970574163248671989632304224237413607995767456077106004328588006429632530124
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011650003 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfc0e9c50, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10011650003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```