PATTGEN Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	145.498us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	58.291us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	18.082us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	292.725us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	28.311us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	50.878us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	18.082us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.311us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.717m	23.202ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.950m	10.527ms	50	50	100.00
V2	error	pattgen_error	4.000s	15.821us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.450m	11.071ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	30.296us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	40.352us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	79.139us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	79.139us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	58.291us	5	5	100.00
		pattgen_csr_rw	4.000s	18.082us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.311us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	63.094us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	58.291us	5	5	100.00
		pattgen_csr_rw	4.000s	18.082us	20	20	100.00
		pattgen_csr_aliasing	3.000s	28.311us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	63.094us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	321.883us	20	20	100.00
		pattgen_sec_cm	3.000s	87.939us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	321.883us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	32.733m	79.666ms	20	50	40.00
V3		TOTAL			20	50	40.00
	Unmapped tests	pattgen_inactive_level	1.467m	10.017ms	46	50	92.00
		TOTAL			536	570	94.04

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:

Test pattgen_stress_all_with_rand_reset has 27 failures.

0.pattgen_stress_all_with_rand_reset.99786448390910176620037341650039745490555672231193957586374885456822940324713
Line 329, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15673370186 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 15673381397 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15673381397 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 15673464731 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.92609594632237559459656798614552398432038446362648638515295807045121623561194
Line 560, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11551268019 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11551278059 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11551278059 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 11551372793 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 25 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 3 failures:
- Test pattgen_stress_all_with_rand_reset has 3 failures.
  - 9.pattgen_stress_all_with_rand_reset.102778256634931903047466251922171330307829847624183603278234194403176435023280
    Line 404, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 6254958326 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 16.pattgen_stress_all_with_rand_reset.18576438568353874596156260090000775100145762045663899548708395100589313225522
    Line 1202, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/16.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 225695117548 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 23.pattgen_inactive_level.90534608433894034873623844249211323107126944747103455851571191434158121206446
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10094653196 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xecce2150, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10094653196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.pattgen_inactive_level.97494014191357651091145814740506565205304096530802685387897924515693854321933
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/43.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016604826 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd9f27e10, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10016604826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 2.pattgen_inactive_level.40013560986709319220672774015383569900160151985190926143058215817814577162043
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10109440304 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe8981710, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10109440304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 49.pattgen_inactive_level.11127225441444989942103983594744330887805267750648231142379917961866174559854
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10019425792 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf5fd58d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10019425792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```