PATTGEN Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	98.677us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	15.345us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	35.052us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	164.088us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	81.138us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	70.234us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	35.052us	20	20	100.00
		pattgen_csr_aliasing	2.000s	81.138us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.883m	6.265ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.817m	5.844ms	50	50	100.00
V2	error	pattgen_error	3.000s	48.493us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.900m	5.745ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	96.806us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	18.395us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	117.717us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	117.717us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	15.345us	5	5	100.00
		pattgen_csr_rw	3.000s	35.052us	20	20	100.00
		pattgen_csr_aliasing	2.000s	81.138us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	63.340us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	15.345us	5	5	100.00
		pattgen_csr_rw	3.000s	35.052us	20	20	100.00
		pattgen_csr_aliasing	2.000s	81.138us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	63.340us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	49.521us	20	20	100.00
		pattgen_sec_cm	2.000s	308.023us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	49.521us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	42.650m	184.417ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	2.717m	10.010ms	47	50	94.00
		TOTAL			532	570	93.33

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

0.pattgen_stress_all_with_rand_reset.46013551713443507901372890139660699500249925924421163495163298348295384868875
Line 485, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28075816344 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 28075839234 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 28075839234 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 28076111964 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.40576721790684166490934392802530873833884286366810376542665872943271269108805
Line 504, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11392350724 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11392356699 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11392356699 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 11392407204 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 5 failures:
- Test pattgen_stress_all_with_rand_reset has 5 failures.
  - 9.pattgen_stress_all_with_rand_reset.104930515815244080371899730392002495792751251589401538796019172426863610266806
    Line 366, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44337957830 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 17.pattgen_stress_all_with_rand_reset.98614207583924555820162437929702720448109546606945076950897832202118874944842
    Line 547, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 30722037635 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 3 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 24.pattgen_inactive_level.64796691508682115369147926041807546481266710355994951694869160303619804038068
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10007211626 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf1dd3d50, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10007211626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.pattgen_inactive_level.63489618532085258787679141738257914736816324305503433591802734101104135900942
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10041487872 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x10198310, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10041487872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 22.pattgen_inactive_level.35978793451235919721007049582613607449202919150199046951694112955178660005545
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/22.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009940351 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4bdefa50, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10009940351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```