PATTGEN Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	4.000s	268.078us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	19.048us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	11.452us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	200.332us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	30.936us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	103.547us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	11.452us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.936us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.767m	23.215ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.967m	2.744ms	50	50	100.00
V2	error	pattgen_error	3.000s	53.417us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.833m	16.754ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.836us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	21.215us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	159.779us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	159.779us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	19.048us	5	5	100.00
		pattgen_csr_rw	2.000s	11.452us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.936us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	71.331us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	19.048us	5	5	100.00
		pattgen_csr_rw	2.000s	11.452us	20	20	100.00
		pattgen_csr_aliasing	3.000s	30.936us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	71.331us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	115.239us	20	20	100.00
		pattgen_sec_cm	3.000s	401.469us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	115.239us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	46.750m	521.646ms	12	50	24.00
V3		TOTAL			12	50	24.00
	Unmapped tests	pattgen_inactive_level	1.900m	10.002ms	46	50	92.00
		TOTAL			528	570	92.63

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

1.pattgen_stress_all_with_rand_reset.64386391142769830964683472899274827726170029478747909466781116404365162528776
Line 558, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12830741550 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 12830742833 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 12830742833 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 12830784501 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.52114448374295033471223532884389806013714071731877039359221238724958043568111
Line 1408, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 150608123692 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 150608136696 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 150608136696 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 10/10
  UVM_INFO @ 150608316696 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 2.pattgen_stress_all_with_rand_reset.79932466174202007850224596227183961808209973863778678221071984247644608994707
    Line 1064, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 267060548632 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 9.pattgen_stress_all_with_rand_reset.45187482400581056427108304815381075295367185128780740394373139671415835642484
    Line 660, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 47260311241 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 27.pattgen_inactive_level.47024702334658115676291673799121056091588717411934420826231069462952171077646
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10001505288 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xda072b10, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10001505288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.pattgen_inactive_level.47387553854503276206477471304499816967397435329161479980758629063663377536300
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006487115 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1ec07d90, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10006487115 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 2.pattgen_inactive_level.96467617174372980478649600984724916282785807299047933295272687501051064558870
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10465793740 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfead3d90, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10465793740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 34.pattgen_inactive_level.2597176950361443990088866866699298683848785638656078189958803460199367181820
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10026660507 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xfeab1050, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10026660507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```