PATTGEN Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	25.212us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	46.393us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	15.199us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	516.940us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	55.808us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	10.000s	56.878us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	15.199us	20	20	100.00
		pattgen_csr_aliasing	3.000s	55.808us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.883m	10.975ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.033m	52.592ms	50	50	100.00
V2	error	pattgen_error	7.000s	186.924us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.633m	13.262ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	99.170us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	52.108us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	140.431us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	140.431us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	46.393us	5	5	100.00
		pattgen_csr_rw	7.000s	15.199us	20	20	100.00
		pattgen_csr_aliasing	3.000s	55.808us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	20.025us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	46.393us	5	5	100.00
		pattgen_csr_rw	7.000s	15.199us	20	20	100.00
		pattgen_csr_aliasing	3.000s	55.808us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	20.025us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	44.750us	20	20	100.00
		pattgen_sec_cm	4.000s	54.909us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	44.750us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	45.667m	633.533ms	17	50	34.00
V3		TOTAL			17	50	34.00
	Unmapped tests	pattgen_inactive_level	5.433m	10.033ms	47	50	94.00
		TOTAL			534	570	93.68

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 31 failures:

Test pattgen_stress_all_with_rand_reset has 31 failures.

1.pattgen_stress_all_with_rand_reset.109436310582654426438302948063868995989914505777801814363655986439233445636426
Line 542, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15681775260 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 15681776008 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 15681776008 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 15681853930 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.38968579891389739761675248610137348105737340239750892283485784907346629381287
Line 676, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 278110967935 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 278111081014 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 278111081014 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 6/10
  UVM_INFO @ 278112581017 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 29 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 4.pattgen_stress_all_with_rand_reset.43102876742261538601520302564753967772565652355926182168909811415520794373994
    Line 785, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 233647496010 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 19.pattgen_stress_all_with_rand_reset.75024808509834452841323977249648751187830269686342272721212559912671139283372
    Line 1405, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 171620445550 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 39.pattgen_inactive_level.88772433884753443018305954187908612699464381003919950982873795429151584491507
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10085109727 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x40696d10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10085109727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.pattgen_inactive_level.7869266455011561885001201968694426324843020270766011485320914228355092506698
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10072532894 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x141775d0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10072532894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 8.pattgen_inactive_level.67773884004166371853102565685035943822835093028780332524793459296541689298886
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10033076446 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4d632ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10033076446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```