PATTGEN Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	7.000s	269.293us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	40.162us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	18.658us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	190.744us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	13.254us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	69.540us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	18.658us	20	20	100.00
		pattgen_csr_aliasing	3.000s	13.254us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.933m	10.615ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	37.583ms	50	50	100.00
V2	error	pattgen_error	3.000s	17.746us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.817m	6.634ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	13.737us	50	50	100.00
V2	intr_test	pattgen_intr_test	2.000s	15.855us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	102.712us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	102.712us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	40.162us	5	5	100.00
		pattgen_csr_rw	2.000s	18.658us	20	20	100.00
		pattgen_csr_aliasing	3.000s	13.254us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	121.749us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	40.162us	5	5	100.00
		pattgen_csr_rw	2.000s	18.658us	20	20	100.00
		pattgen_csr_aliasing	3.000s	13.254us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	121.749us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	1.026ms	20	20	100.00
		pattgen_sec_cm	3.000s	56.589us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	1.026ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	35.333m	103.255ms	14	50	28.00
V3		TOTAL			14	50	28.00
	Unmapped tests	pattgen_inactive_level	5.450m	10.010ms	45	50	90.00
		TOTAL			529	570	92.81

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:

Test pattgen_stress_all_with_rand_reset has 30 failures.

3.pattgen_stress_all_with_rand_reset.110780512954420985214133617458288258650707822499809783930466045326823784148834
Line 400, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 13674508656 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 13674522938 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 13674522938 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 13674682938 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.106456609489959321835607004509110603549593663452707402045001600336052164071386
Line 318, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1385125138 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1385127071 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1385127071 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 1385293742 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 28 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 6 failures:
- Test pattgen_stress_all_with_rand_reset has 6 failures.
  - 0.pattgen_stress_all_with_rand_reset.45688706960274873596266181458014470111371810967960510270735999265747851032169
    Line 353, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 19840621508 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 1.pattgen_stress_all_with_rand_reset.71801433661927526820142043192951076040456213828587064187570934484827829686793
    Line 612, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 65250036200 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - ... and 4 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 23.pattgen_inactive_level.99522800146935131389815203730243386865738317671052844256665113826521588057723
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10005887312 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc5c6cad0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10005887312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.pattgen_inactive_level.29599201299761465958471991835235157724180382914994336061706547655763080744520
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009472988 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x64e16090, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10009472988 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=18) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 4.pattgen_inactive_level.48579607076730626707063957449568266631509533326748432778024612332467658998826
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10024426460 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xeaeb07d0, Comparison=CompareOpEq, exp_data=0x0, call_count=18)
  UVM_INFO @ 10024426460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=12) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 7.pattgen_inactive_level.24110957316710877824186735107798917351242821275795654435191379672817843554372
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10019706903 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x80476dd0, Comparison=CompareOpEq, exp_data=0x0, call_count=12)
  UVM_INFO @ 10019706903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 17.pattgen_inactive_level.13296007777137899668635857028463802172888673697143993645626091271500595782256
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/17.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009897167 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xda68310, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10009897167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```