PATTGEN Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	179.781us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	46.170us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	13.007us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	264.217us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	234.344us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	21.427us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	13.007us	20	20	100.00
		pattgen_csr_aliasing	3.000s	234.344us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	2.689ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.950m	5.598ms	50	50	100.00
V2	error	pattgen_error	8.000s	53.269us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.900m	14.530ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	14.741us	50	50	100.00
V2	intr_test	pattgen_intr_test	8.000s	11.798us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	205.205us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	205.205us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	46.170us	5	5	100.00
		pattgen_csr_rw	7.000s	13.007us	20	20	100.00
		pattgen_csr_aliasing	3.000s	234.344us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	59.515us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	46.170us	5	5	100.00
		pattgen_csr_rw	7.000s	13.007us	20	20	100.00
		pattgen_csr_aliasing	3.000s	234.344us	5	5	100.00
		pattgen_same_csr_outstanding	7.000s	59.515us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	87.559us	20	20	100.00
		pattgen_sec_cm	3.000s	281.837us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	87.559us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	22.217m	406.674ms	15	50	30.00
V3		TOTAL			15	50	30.00
	Unmapped tests	pattgen_inactive_level	5.983m	10.004ms	46	50	92.00
		TOTAL			531	570	93.16

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 33 failures:

Test pattgen_stress_all_with_rand_reset has 33 failures.

1.pattgen_stress_all_with_rand_reset.74757901142769033256818313037451037542794917334150924071903735280899638394885
Line 1251, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 73467159797 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 73467173258 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 73467173258 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 9/10
  UVM_INFO @ 73467275298 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

4.pattgen_stress_all_with_rand_reset.114639732351131311374372840147835227694485057853090311037309826164173511734379
Line 493, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30526916007 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 30526920171 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 30526920171 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 30527311473 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 31 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 19.pattgen_stress_all_with_rand_reset.17941802916399656491500583619371643688245079099895257563703207676824762749156
    Line 355, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9814874521 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 31.pattgen_stress_all_with_rand_reset.52948305415974801608444627776934060116472086679960481472040678295199767278719
    Line 744, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/31.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 56972042629 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 3.pattgen_inactive_level.115198406556768748973731747918294282119967279123905781378896371026804144047724
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10022173062 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe63c5cd0, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10022173062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 20.pattgen_inactive_level.74387818204909883759130947279440588481991214751623470921275514594393229852407
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/20.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003875466 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb6a0a9d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10003875466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 24.pattgen_inactive_level.28742188095771751097074846228934957694543333010904258240816163091956808209892
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10001920105 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x55b78750, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10001920105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.36498789687287395085762005096636525021675831576218870696512365615435985934680
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10011443076 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x28fda390, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10011443076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```