PATTGEN Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	178.951us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	26.617us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	23.444us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	845.934us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	56.396us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	26.628us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	23.444us	20	20	100.00
		pattgen_csr_aliasing	2.000s	56.396us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.833m	4.201ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.867m	2.621ms	50	50	100.00
V2	error	pattgen_error	7.000s	23.368us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.933m	16.423ms	50	50	100.00
V2	alert_test	pattgen_alert_test	14.000s	37.408us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	29.801us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	18.000s	50.906us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	18.000s	50.906us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	26.617us	5	5	100.00
		pattgen_csr_rw	7.000s	23.444us	20	20	100.00
		pattgen_csr_aliasing	2.000s	56.396us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	28.233us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	26.617us	5	5	100.00
		pattgen_csr_rw	7.000s	23.444us	20	20	100.00
		pattgen_csr_aliasing	2.000s	56.396us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	28.233us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	13.000s	66.753us	20	20	100.00
		pattgen_sec_cm	2.000s	241.473us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	13.000s	66.753us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	36.017m	102.706ms	13	50	26.00
V3		TOTAL			13	50	26.00
	Unmapped tests	pattgen_inactive_level	1.467m	10.014ms	44	50	88.00
		TOTAL			527	570	92.46

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:837) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 34 failures:

Test pattgen_stress_all_with_rand_reset has 34 failures.

2.pattgen_stress_all_with_rand_reset.76316153552953687265320664817999262423245849758491288138918336836165903318404
Line 397, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4925239486 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4925241244 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4925241244 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 4925293874 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

3.pattgen_stress_all_with_rand_reset.33659796693494442128400607362591963450068334692300055712543556026993521361923
Line 296, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5782379154 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5782399536 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5782399536 ps: (cip_base_vseq.sv:759) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 5782677316 ps: (cip_base_vseq.sv:768) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 32 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 5.pattgen_inactive_level.100576047767250428458889236179397758097509557826198063223075153290800927526317
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010900789 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x780221d0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10010900789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.pattgen_inactive_level.70505899864548378599947464082605690141487502922860868228089532609531774262255
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10029967377 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x78c5c510, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10029967377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 9.pattgen_stress_all_with_rand_reset.52502580912179126246584381423724904005505037524480401428791254161143397328349
    Line 425, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 25517570802 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 46.pattgen_stress_all_with_rand_reset.34477791331222833564290301205387806811989004642387329864216425686416107631264
    Line 571, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/46.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 14430925318 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_ERROR (pattgen_scoreboard.sv:249) [scoreboard] exp_item_q[i] item uncompared: has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 5.pattgen_stress_all_with_rand_reset.46242794340118327383122122527170893200363272625019925756641344564541287076452
    Line 1569, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/5.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1419872992211 ps: (pattgen_scoreboard.sv:249) [uvm_test_top.env.scoreboard] exp_item_q[i] item uncompared:
  ------------------------------------
  Name      Type          Size  Value
  ------------------------------------
  exp_item  pattgen_item  -     @12814
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 27.pattgen_inactive_level.48048954556851451829111219127729398926273177860603553139986225170136783509170
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/27.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10139968377 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8d3f8f50, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10139968377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 28.pattgen_inactive_level.94674903555007317891635492904915308966804807176251152553304544764462698633194
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10032771691 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x72a99310, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10032771691 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 45.pattgen_inactive_level.78057179566758723638161209695493782696089469711415678971368987725591645365114
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/45.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013936179 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x51d71e50, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10013936179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 48.pattgen_inactive_level.98024853870498566572766874350748686807766639133357933861067505260395265579549
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10193893628 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8c433d90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10193893628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```