PATTGEN Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	165.679us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	15.730us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	54.369us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	3.000s	134.289us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	24.794us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	25.942us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	54.369us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.794us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.933m	3.661ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.783m	2.583ms	50	50	100.00
V2	error	pattgen_error	3.000s	128.936us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.833m	8.113ms	50	50	100.00
V2	alert_test	pattgen_alert_test	2.000s	12.284us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	46.800us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	277.089us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	277.089us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	15.730us	5	5	100.00
		pattgen_csr_rw	3.000s	54.369us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.794us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	59.795us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	15.730us	5	5	100.00
		pattgen_csr_rw	3.000s	54.369us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.794us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	59.795us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	1.307ms	20	20	100.00
		pattgen_sec_cm	3.000s	64.464us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	1.307ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	4.400m	22.278ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	5.583m	10.002ms	44	50	88.00
		TOTAL			515	570	90.35

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:849) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:

Test pattgen_stress_all_with_rand_reset has 47 failures.

0.pattgen_stress_all_with_rand_reset.67738756663263082127139011386476134182880822346413122767341024955579409644662
Line 307, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 949719051 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 949729149 ps: (cip_base_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 949729149 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 949781779 ps: (cip_base_vseq.sv:780) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.82921010638454352521017034267830062045945297379534849956322766630149328082735
Line 296, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1739989216 ps: (cip_base_vseq.sv:849) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1739994001 ps: (cip_base_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1739994001 ps: (cip_base_vseq.sv:771) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1740034817 ps: (cip_base_vseq.sv:780) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 45 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 4.pattgen_stress_all_with_rand_reset.75341242882720364141637854743673180859349418866335114278154648306848596074442
    Line 360, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9817279378 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 30.pattgen_stress_all_with_rand_reset.18409226045452621309934555808389806712010520364420869940759048657395715748912
    Line 309, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 310869878 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 6.pattgen_inactive_level.47322912914739704403963460960443874308469047180421160631659688792048413501860
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10061115556 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x42b2e850, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10061115556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.pattgen_inactive_level.27849269226872479255489683941110494772352314058488734213242802584257202681692
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/19.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10015832176 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xbf6e4110, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10015832176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=20) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 0.pattgen_inactive_level.11584026168644188353660371156539829957565235070758435697307712931396046637222
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10018669667 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcd0954d0, Comparison=CompareOpEq, exp_data=0x0, call_count=20)
  UVM_INFO @ 10018669667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 9.pattgen_inactive_level.72728620681104348094991504053959007004061971478976376122291766750672986138611
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10020041572 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x979e3d90, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10020041572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 15.pattgen_inactive_level.60673477994677530833618717510699353147226359465334762904798951606424014587350
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003171629 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x41e41690, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10003171629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 29.pattgen_inactive_level.33769032833305462804128519263710543927934551052873412903593691063169942248493
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/29.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002353204 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x634350, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10002353204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```