PATTGEN Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: `098010d125`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	694.665us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	18.215us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	24.003us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.080ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	33.034us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	29.948us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	24.003us	20	20	100.00
		pattgen_csr_aliasing	2.000s	33.034us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.700m	8.218ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.833m	43.813ms	50	50	100.00
V2	error	pattgen_error	3.000s	94.435us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.817m	5.561ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	36.408us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	46.546us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	168.094us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	168.094us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	18.215us	5	5	100.00
		pattgen_csr_rw	2.000s	24.003us	20	20	100.00
		pattgen_csr_aliasing	2.000s	33.034us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	35.503us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	18.215us	5	5	100.00
		pattgen_csr_rw	2.000s	24.003us	20	20	100.00
		pattgen_csr_aliasing	2.000s	33.034us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	35.503us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	305.579us	20	20	100.00
		pattgen_sec_cm	3.000s	112.545us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	305.579us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	4.417m	6.245ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	19.000s	10.083ms	48	50	96.00
		TOTAL			521	570	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:

Test pattgen_stress_all_with_rand_reset has 46 failures.

0.pattgen_stress_all_with_rand_reset.83035905226573130826508654323449339244599515589181678242695386228520207120686
Line 358, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1858954752 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1858955942 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1858955942 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 1859080943 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.22988932265731631566034184412415225427965059700490527242238444844991899795983
Line 357, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1159878730 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1159883989 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1159883989 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 1159943989 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 44 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 13.pattgen_inactive_level.39735935258952708512775871764291756179050947977542953492348584547555682372551
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/13.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10337762758 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xafd3e050, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10337762758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.91380537746257939866267152343907053381653515453910701608906108451088204812791
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10083084999 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xccd54050, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10083084999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 47.pattgen_stress_all_with_rand_reset.18268489756503773112180378592854694876762276962229687911485238341705162771891
    Line 314, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 382865079 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```