PATTGEN Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	12.000s	58.904us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	17.431us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	12.000s	51.211us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	236.610us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	18.121us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	9.000s	26.743us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	12.000s	51.211us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.121us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.750m	3.990ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.067m	5.431ms	50	50	100.00
V2	error	pattgen_error	7.000s	28.087us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.850m	16.699ms	50	50	100.00
V2	alert_test	pattgen_alert_test	13.000s	12.404us	50	50	100.00
V2	intr_test	pattgen_intr_test	7.000s	23.676us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	15.000s	139.310us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	15.000s	139.310us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	17.431us	5	5	100.00
		pattgen_csr_rw	12.000s	51.211us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.121us	5	5	100.00
		pattgen_same_csr_outstanding	13.000s	22.904us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	17.431us	5	5	100.00
		pattgen_csr_rw	12.000s	51.211us	20	20	100.00
		pattgen_csr_aliasing	3.000s	18.121us	5	5	100.00
		pattgen_same_csr_outstanding	13.000s	22.904us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	13.000s	155.099us	20	20	100.00
		pattgen_sec_cm	3.000s	64.084us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	13.000s	155.099us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.233m	4.320ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	1.400m	10.014ms	46	50	92.00
		TOTAL			519	570	91.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:

Test pattgen_stress_all_with_rand_reset has 47 failures.

0.pattgen_stress_all_with_rand_reset.12646709135344865360682266174239176408283337120642747624987081190928766374792
Line 293, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 489532344 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 489533043 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 489533043 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 489637213 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.92226648628289267033935297318822060254246849264189966729800426105133754965404
Line 352, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4504894086 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4504944264 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4504944264 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 4505244264 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 45 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 18.pattgen_inactive_level.72483071175786063382042420033197858203737645238668029254751958387049737000139
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10022367374 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xf0fdde50, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10022367374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 26.pattgen_inactive_level.94170782272483827211571379314799124648125146549166121686544382755768508403148
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10021408339 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x5fb43110, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10021408339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 44.pattgen_inactive_level.38802299371101840033373329108922847806967126821184100578721343752486985071080
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010437309 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9cad3590, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10010437309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 48.pattgen_inactive_level.89516857297189805666169235259480259652931673185923216905772467542242063151556
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/48.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013558643 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb9aa0050, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10013558643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```