PATTGEN Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	191.868us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	46.005us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	7.000s	45.317us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	10.000s	3.007ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	7.000s	13.912us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	29.276us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	7.000s	45.317us	20	20	100.00
		pattgen_csr_aliasing	7.000s	13.912us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.033m	24.105ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	10.964ms	50	50	100.00
V2	error	pattgen_error	12.000s	25.643us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.483m	8.016ms	50	50	100.00
V2	alert_test	pattgen_alert_test	12.000s	30.605us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	16.387us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	8.000s	71.283us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	8.000s	71.283us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	46.005us	5	5	100.00
		pattgen_csr_rw	7.000s	45.317us	20	20	100.00
		pattgen_csr_aliasing	7.000s	13.912us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	105.239us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	46.005us	5	5	100.00
		pattgen_csr_rw	7.000s	45.317us	20	20	100.00
		pattgen_csr_aliasing	7.000s	13.912us	5	5	100.00
		pattgen_same_csr_outstanding	8.000s	105.239us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	40.035us	20	20	100.00
		pattgen_sec_cm	2.000s	31.100us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	40.035us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.667m	68.341ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	1.850m	10.002ms	45	50	90.00
		TOTAL			516	570	90.53

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:

Test pattgen_stress_all_with_rand_reset has 48 failures.

0.pattgen_stress_all_with_rand_reset.4285351555669138887732441683723644508269317859942101966157421311603824635805
Line 408, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3149742936 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3149757204 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3149757204 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 3150047526 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.244699491458492009893157664717369477068140368981691508019905507447960206805
Line 353, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1597222565 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1597230762 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1597230762 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 1597281267 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 46 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 44.pattgen_inactive_level.92584173902807513625851536514398337104628179593002026191141404873573042248500
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/44.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10847316654 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc6ed1490, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
  UVM_INFO @ 10847316654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.pattgen_inactive_level.66236750263059512173813946118918404708600677910715344183070574746510997362301
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10149598915 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xada98050, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
  UVM_INFO @ 10149598915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 4.pattgen_inactive_level.97695709209778873317829877730098072093458253063668629644833181979760431772405
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/4.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10001598284 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb6d2b190, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10001598284 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.99575730476017245441732265579750745631536244964564415194652264298582073449878
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10072157418 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc49d39d0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10072157418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 32.pattgen_stress_all_with_rand_reset.65498678539263251362086245322843113626077283082732716663069704755918852586751
    Line 311, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/32.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 175035855 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 42.pattgen_inactive_level.112789633206526402029568630436837762299266077727778465792296036771442941742521
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10412453849 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xfc033f90, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
  UVM_INFO @ 10412453849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```