PATTGEN Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	12.000s	56.456us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	30.084us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000s	13.780us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	4.000s	125.768us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	50.172us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	269.831us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000s	13.780us	20	20	100.00
		pattgen_csr_aliasing	2.000s	50.172us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.917m	9.748ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.933m	10.524ms	50	50	100.00
V2	error	pattgen_error	12.000s	31.476us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.683m	5.516ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	13.795us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	22.169us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	91.413us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	91.413us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	30.084us	5	5	100.00
		pattgen_csr_rw	2.000s	13.780us	20	20	100.00
		pattgen_csr_aliasing	2.000s	50.172us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	16.654us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	30.084us	5	5	100.00
		pattgen_csr_rw	2.000s	13.780us	20	20	100.00
		pattgen_csr_aliasing	2.000s	50.172us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	16.654us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.000s	54.680us	20	20	100.00
		pattgen_sec_cm	3.000s	352.454us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.000s	54.680us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.383m	13.016ms	2	50	4.00
V3		TOTAL			2	50	4.00
	Unmapped tests	pattgen_inactive_level	5.417m	10.007ms	47	50	94.00
		TOTAL			519	570	91.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:

Test pattgen_stress_all_with_rand_reset has 48 failures.

1.pattgen_stress_all_with_rand_reset.39354366873409014033132918278962852794280970726231264898677152355625017456435
Line 352, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5156798832 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 5156802662 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 5156802662 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 5157052662 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.105085800818335622546413379786957313997032958882448638143009040033708310375800
Line 331, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3060387044 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3060399049 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3060399049 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 3060499049 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 46 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 7.pattgen_inactive_level.60512178930839310160153091698436373443443596186422705909961508686725633162946
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10007337554 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd27baf10, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10007337554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.pattgen_inactive_level.101780403934895854582705003929856306940440434401167816297756884443847636305624
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/39.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016030337 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x25575d90, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10016030337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=27) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 23.pattgen_inactive_level.101703015672684118308183931845138112179375312366810215723499302043552963498282
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/23.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10359015400 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9c3929d0, Comparison=CompareOpEq, exp_data=0x0, call_count=27)
  UVM_INFO @ 10359015400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```