PATTGEN Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	13.000s	42.283us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	7.000s	15.168us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	12.298us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	750.882us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	12.000s	29.321us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	8.000s	34.048us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	12.298us	20	20	100.00
		pattgen_csr_aliasing	12.000s	29.321us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.033m	6.588ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.883m	2.689ms	50	50	100.00
V2	error	pattgen_error	18.000s	50.307us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.767m	8.188ms	50	50	100.00
V2	alert_test	pattgen_alert_test	8.000s	14.725us	50	50	100.00
V2	intr_test	pattgen_intr_test	12.000s	40.345us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	6.000s	185.651us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	6.000s	185.651us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	7.000s	15.168us	5	5	100.00
		pattgen_csr_rw	3.000s	12.298us	20	20	100.00
		pattgen_csr_aliasing	12.000s	29.321us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	22.800us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	7.000s	15.168us	5	5	100.00
		pattgen_csr_rw	3.000s	12.298us	20	20	100.00
		pattgen_csr_aliasing	12.000s	29.321us	5	5	100.00
		pattgen_same_csr_outstanding	12.000s	22.800us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	17.000s	172.427us	20	20	100.00
		pattgen_sec_cm	7.000s	690.956us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	17.000s	172.427us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.100m	8.150ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	2.683m	10.005ms	47	50	94.00
		TOTAL			520	570	91.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:

Test pattgen_stress_all_with_rand_reset has 46 failures.

0.pattgen_stress_all_with_rand_reset.107318381246306477970182376200282778402080438283889497465539638792994791507271
Line 321, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1093214094 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1093217992 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1093217992 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1093238826 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.101274687307103263850588051984826817382373471376371373396855203422804455979603
Line 299, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1323238057 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1323258299 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1323258299 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1323320798 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 44 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 7.pattgen_inactive_level.79124916133742907031833292379206032164046722669682434977097184402920558476076
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/7.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013819084 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa300c650, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10013819084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 14.pattgen_inactive_level.25398173352624608840502954052172448727340929979094592485203720898916677781677
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004826371 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x89f06c50, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10004826371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 15.pattgen_stress_all_with_rand_reset.95977023767872776759700600451242371917583176688660148879041883971377854658837
    Line 342, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/15.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 537748822 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.84731321861793492996630618717507178095609514975377168480510254729608362834272
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008656516 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x4c4b5090, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10008656516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```