PATTGEN Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	173.938us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	2.000s	15.180us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	25.030us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.554ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	119.637us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	3.000s	69.644us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	25.030us	20	20	100.00
		pattgen_csr_aliasing	3.000s	119.637us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	3.033m	8.218ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	2.620ms	50	50	100.00
V2	error	pattgen_error	7.000s	30.700us	50	50	100.00
V2	stress_all	pattgen_stress_all	5.000m	26.389ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	40.372us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	17.624us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	438.920us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	438.920us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	2.000s	15.180us	5	5	100.00
		pattgen_csr_rw	3.000s	25.030us	20	20	100.00
		pattgen_csr_aliasing	3.000s	119.637us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	17.398us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	2.000s	15.180us	5	5	100.00
		pattgen_csr_rw	3.000s	25.030us	20	20	100.00
		pattgen_csr_aliasing	3.000s	119.637us	5	5	100.00
		pattgen_same_csr_outstanding	3.000s	17.398us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	275.485us	20	20	100.00
		pattgen_sec_cm	2.000s	85.285us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	275.485us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	4.533m	16.737ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	43.000s	10.014ms	49	50	98.00
		TOTAL			520	570	91.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 49 failures:

Test pattgen_stress_all_with_rand_reset has 49 failures.

0.pattgen_stress_all_with_rand_reset.102319605755503149337931716502055094669171046805200845274926482664446672669430
Line 326, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3485602767 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 3485645927 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3485645927 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 3485979262 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.105475986243196186807491486382077640972679911315699817493888164765499054530003
Line 296, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1026580664 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1026589449 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1026589449 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1026610067 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 47 more failures.

Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 18.pattgen_inactive_level.11749898359881711175176950566204815601347431220666164572819355719164734504289
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/18.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10014350280 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3ff0e690, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10014350280 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```