PATTGEN Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	9.000s	689.264us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	9.000s	16.967us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	5.000s	16.123us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	1.178ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.000s	24.802us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	17.000s	31.526us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	5.000s	16.123us	20	20	100.00
		pattgen_csr_aliasing	2.000s	24.802us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.950m	8.054ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.850m	2.635ms	50	50	100.00
V2	error	pattgen_error	3.000s	91.373us	50	50	100.00
V2	stress_all	pattgen_stress_all	3.617m	5.413ms	50	50	100.00
V2	alert_test	pattgen_alert_test	7.000s	16.524us	50	50	100.00
V2	intr_test	pattgen_intr_test	17.000s	13.550us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	9.000s	147.671us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	9.000s	147.671us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	9.000s	16.967us	5	5	100.00
		pattgen_csr_rw	5.000s	16.123us	20	20	100.00
		pattgen_csr_aliasing	2.000s	24.802us	5	5	100.00
		pattgen_same_csr_outstanding	11.000s	60.534us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	9.000s	16.967us	5	5	100.00
		pattgen_csr_rw	5.000s	16.123us	20	20	100.00
		pattgen_csr_aliasing	2.000s	24.802us	5	5	100.00
		pattgen_same_csr_outstanding	11.000s	60.534us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	8.000s	218.021us	20	20	100.00
		pattgen_sec_cm	2.000s	67.684us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	8.000s	218.021us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.000m	18.124ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	1.400m	10.059ms	47	50	94.00
		TOTAL			520	570	91.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:

Test pattgen_stress_all_with_rand_reset has 46 failures.

0.pattgen_stress_all_with_rand_reset.69603082289008174694656854973341809734730539826217191262132657892465177514957
Line 375, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4634481278 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 4634483510 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 4634483510 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 4634744378 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.87100328639370220863067099170491777758468751439794667827955097457059971272618
Line 290, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 105936664 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 105945164 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 105945164 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 105965366 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 44 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 6.pattgen_inactive_level.78469154172508795220622331620008736163616601628338005531267652456475245036836
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10046941606 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x61f5fe10, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10046941606 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 24.pattgen_inactive_level.94518120365072919174033777379409145620320537365267305785154583675521191828722
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 12569865927 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x5a20ccd0, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
  UVM_INFO @ 12569865927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 36.pattgen_inactive_level.15503563856520626452170852817308471393763878141313239745928859996365916425493
    Line 276, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10059314086 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb52ea690, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10059314086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 38.pattgen_stress_all_with_rand_reset.78808100160747216643942282624299809991996723965884870099005037166421190640826
    Line 315, in log /container/opentitan-public/scratch/os_regression/pattgen-sim-xcelium/38.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 274856702 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```