PATTGEN Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.000m	93.956us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	6.000s	23.996us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.350m	21.427us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	10.000s	139.089us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	9.000s	171.746us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.683m	26.144us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.350m	21.427us	20	20	100.00
		pattgen_csr_aliasing	9.000s	171.746us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.567m	6.470ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.067m	2.635ms	50	50	100.00
V2	error	pattgen_error	52.000s	49.661us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.750m	4.340ms	50	50	100.00
V2	alert_test	pattgen_alert_test	38.000s	106.861us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.483m	86.917us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.517m	52.752us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.517m	52.752us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	6.000s	23.996us	5	5	100.00
		pattgen_csr_rw	1.350m	21.427us	20	20	100.00
		pattgen_csr_aliasing	9.000s	171.746us	5	5	100.00
		pattgen_same_csr_outstanding	1.383m	122.765us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	6.000s	23.996us	5	5	100.00
		pattgen_csr_rw	1.350m	21.427us	20	20	100.00
		pattgen_csr_aliasing	9.000s	171.746us	5	5	100.00
		pattgen_same_csr_outstanding	1.383m	122.765us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.367m	182.821us	20	20	100.00
		pattgen_sec_cm	3.000s	271.215us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.367m	182.821us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.833m	10.475ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	4.683m	10.067ms	49	50	98.00
		TOTAL			520	570	91.23

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:

Test pattgen_stress_all_with_rand_reset has 48 failures.

0.pattgen_stress_all_with_rand_reset.59810731641613994562465357304073718383607314271595768395024581109051408522582
Line 115, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1964739690 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1964747301 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1964747301 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 1964820029 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.99951387621237534442461964189777548058718010042974281831409741802258260976046
Line 169, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 11225639056 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 11225688499 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 11225688499 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 11226831355 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 46 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 30.pattgen_inactive_level.83192021296181992323570939051117444164911851657317174955874937215027583744458
    Line 89, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pattgen-sim-xcelium/30.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10067293101 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9b0291d0, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
  UVM_INFO @ 10067293101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 36.pattgen_stress_all_with_rand_reset.25777453033162483551151363475264189221825391379587126642148178096015964382753
    Line 145, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/pattgen-sim-xcelium/36.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 911337239 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```