PATTGEN Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	10.000s	817.461us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	40.965us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	42.196us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	5.000s	754.240us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	3.000s	24.708us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	27.247us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	42.196us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.708us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.500m	15.784ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.717m	2.687ms	50	50	100.00
V2	error	pattgen_error	4.000s	42.648us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.467m	4.118ms	50	50	100.00
V2	alert_test	pattgen_alert_test	3.000s	74.854us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	27.893us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	5.000s	40.334us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	5.000s	40.334us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	40.965us	5	5	100.00
		pattgen_csr_rw	3.000s	42.196us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.708us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	32.165us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	40.965us	5	5	100.00
		pattgen_csr_rw	3.000s	42.196us	20	20	100.00
		pattgen_csr_aliasing	3.000s	24.708us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	32.165us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	281.677us	20	20	100.00
		pattgen_sec_cm	3.000s	130.248us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	281.677us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.800m	3.948ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	4.183m	10.027ms	45	50	90.00
		TOTAL			518	570	90.88

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 47 failures:

Test pattgen_stress_all_with_rand_reset has 47 failures.

0.pattgen_stress_all_with_rand_reset.54316914485118036118104218342872335129754584203982676646736717031775879963205
Line 103, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 211747966 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 211748263 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 211748263 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 211850303 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.31249851286702256736797141992328149146884240641283588703850376901554204743058
Line 202, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14550594004 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 14550606100 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 14550606100 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/5
  UVM_INFO @ 14551298407 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 45 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=25) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 1.pattgen_inactive_level.105305122454949419522226010771901614074399184825218122261895400782171978302019
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10163311326 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x70ce52d0, Comparison=CompareOpEq, exp_data=0x0, call_count=25)
  UVM_INFO @ 10163311326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 6.pattgen_inactive_level.78615143408721223313499623883245674371723752849813411456745263558425087781076
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10021461294 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x8ab459d0, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10021461294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 9.pattgen_inactive_level.16895147722122809073974032083478485519458478369936675665448861320502645110747
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10027454806 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xd31d9450, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10027454806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=17) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 14.pattgen_inactive_level.68376486251076825511491353207929483197416656860329274437294714135362806615479
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10035087347 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xe3e42910, Comparison=CompareOpEq, exp_data=0x0, call_count=17)
  UVM_INFO @ 10035087347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=21) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.96256120028906518504967628769286755345967057500550084618152290036775243367272
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_22/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013394572 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x975dd810, Comparison=CompareOpEq, exp_data=0x0, call_count=21)
  UVM_INFO @ 10013394572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```