PATTGEN Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: XCELIUM

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.950m	156.644us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	3.000s	27.772us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	4.000s	12.758us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	6.000s	3.736ms	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	30.668us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	19.173us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	4.000s	12.758us	20	20	100.00
		pattgen_csr_aliasing	4.000s	30.668us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	3.767m	3.949ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.167m	1.229ms	50	50	100.00
V2	error	pattgen_error	1.567m	130.047us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.317m	14.012ms	50	50	100.00
V2	alert_test	pattgen_alert_test	1.733m	21.552us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.000s	15.642us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	7.000s	195.927us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	7.000s	195.927us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	3.000s	27.772us	5	5	100.00
		pattgen_csr_rw	4.000s	12.758us	20	20	100.00
		pattgen_csr_aliasing	4.000s	30.668us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	28.595us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	3.000s	27.772us	5	5	100.00
		pattgen_csr_rw	4.000s	12.758us	20	20	100.00
		pattgen_csr_aliasing	4.000s	30.668us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	28.595us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	100.819us	20	20	100.00
		pattgen_sec_cm	3.000s	239.976us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	100.819us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.250m	5.088ms	3	50	6.00
V3		TOTAL			3	50	6.00
	Unmapped tests	pattgen_inactive_level	6.167m	10.003ms	46	50	92.00
		TOTAL			519	570	91.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 45 failures:

Test pattgen_stress_all_with_rand_reset has 45 failures.

1.pattgen_stress_all_with_rand_reset.62348697696583353573738218141871055078856844428819440635671225973520184907725
Line 115, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6299259953 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6299280924 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6299280924 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 6299917287 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.87951105753999388470575949168537076807726851330116618397198763758718213574672
Line 179, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1490817075 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1490824031 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1490824031 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 1490890697 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 43 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 10.pattgen_inactive_level.15611425681286211920342422047547506813325473882971050779653705549966851501734
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/10.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003172037 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xff1c8ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10003172037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.pattgen_inactive_level.110487641806285901709358211624343192426523214409960044585957273515154128490680
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10029135983 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x1a8f52d0, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10029135983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 25.pattgen_stress_all_with_rand_reset.25711913274826736235910703813751474896335785106498522000840730694894697330374
    Line 285, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/25.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1855887656 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 42.pattgen_stress_all_with_rand_reset.50575012930546680429055222894169129747385865879078453834637928051137527276344
    Line 143, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/42.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3273442661 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=16) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 26.pattgen_inactive_level.73069566346413850833237053538230281326850790771618180174491260030458559789800
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10097637099 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xa8159310, Comparison=CompareOpEq, exp_data=0x0, call_count=16)
  UVM_INFO @ 10097637099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 49.pattgen_inactive_level.14363369289134455003371257587496258421745670241095533117933738369371625943274
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_24/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10661464702 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf44dbe50, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10661464702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```