PATTGEN Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: XCELIUM

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	48.000s	184.636us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	9.000s	53.771us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.450m	15.100us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	11.000s	203.462us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	9.000s	143.935us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.933m	67.743us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.450m	15.100us	20	20	100.00
		pattgen_csr_aliasing	9.000s	143.935us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.467m	8.219ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.700m	5.266ms	50	50	100.00
V2	error	pattgen_error	49.000s	17.787us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.567m	16.141ms	50	50	100.00
V2	alert_test	pattgen_alert_test	46.000s	116.944us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.467m	13.805us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.450m	94.681us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.450m	94.681us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	9.000s	53.771us	5	5	100.00
		pattgen_csr_rw	1.450m	15.100us	20	20	100.00
		pattgen_csr_aliasing	9.000s	143.935us	5	5	100.00
		pattgen_same_csr_outstanding	1.533m	69.275us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	9.000s	53.771us	5	5	100.00
		pattgen_csr_rw	1.450m	15.100us	20	20	100.00
		pattgen_csr_aliasing	9.000s	143.935us	5	5	100.00
		pattgen_same_csr_outstanding	1.533m	69.275us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.450m	136.223us	20	20	100.00
		pattgen_sec_cm	3.000s	32.055us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.450m	136.223us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	2.483m	17.588ms	2	50	4.00
V3		TOTAL			2	50	4.00
	Unmapped tests	pattgen_inactive_level	2.300m	10.003ms	45	50	90.00
		TOTAL			517	570	90.70

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 48 failures:

Test pattgen_stress_all_with_rand_reset has 48 failures.

0.pattgen_stress_all_with_rand_reset.61518214407928713437332197598717707885114126980666308468751268249118888372680
Line 205, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1144332932 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1144335177 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1144335177 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 1144407340 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.61405670582997028179516002155747604194664037250852764783727753417059768156324
Line 184, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1331033415 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1331035223 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1331035223 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 3/10
  UVM_INFO @ 1331195223 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 46 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 25.pattgen_inactive_level.36252414989419715314817076728532378669144400321336775675813654318602973557692
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10017803555 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xc53ff850, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10017803555 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.pattgen_inactive_level.28232419229747459812303487943470301420210455695940230855190039230183735598456
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/42.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10006485812 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xafcf7fd0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10006485812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 21.pattgen_inactive_level.111848968310201758492089586178076224573586942287633640190065356889180887578793
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/21.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10033628255 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa5a9e150, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10033628255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=23) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 31.pattgen_inactive_level.101384313633665710622683632638358335467764547688885225774504003837222810244562
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/31.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10134552176 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x9e71e290, Comparison=CompareOpEq, exp_data=0x0, call_count=23)
  UVM_INFO @ 10134552176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 35.pattgen_inactive_level.10631244670031946384441939421986456631103093532860830921674301601226738189792
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_26/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10002965494 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x558b5350, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10002965494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```