PATTGEN Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	1.483m	53.355us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.150m	11.437us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	2.000m	14.674us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	1.417m	488.559us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.600m	36.271us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.167m	56.128us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	2.000m	14.674us	20	20	100.00
		pattgen_csr_aliasing	1.600m	36.271us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.550m	10.526ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.767m	5.539ms	50	50	100.00
V2	error	pattgen_error	1.617m	43.339us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.900m	4.015ms	50	50	100.00
V2	alert_test	pattgen_alert_test	59.000s	12.516us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.600m	29.560us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000m	132.352us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000m	132.352us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.150m	11.437us	5	5	100.00
		pattgen_csr_rw	2.000m	14.674us	20	20	100.00
		pattgen_csr_aliasing	1.600m	36.271us	5	5	100.00
		pattgen_same_csr_outstanding	2.150m	16.999us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.150m	11.437us	5	5	100.00
		pattgen_csr_rw	2.000m	14.674us	20	20	100.00
		pattgen_csr_aliasing	1.600m	36.271us	5	5	100.00
		pattgen_same_csr_outstanding	2.150m	16.999us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	2.000m	87.935us	20	20	100.00
		pattgen_sec_cm	3.000s	57.576us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	2.000m	87.935us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.133m	5.420ms	0	50	0.00
V3		TOTAL			0	50	0.00
	Unmapped tests	pattgen_inactive_level	1.833m	10.004ms	49	50	98.00
		TOTAL			519	570	91.05

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.

has 50 failures:

Test pattgen_stress_all_with_rand_reset has 50 failures.

0.pattgen_stress_all_with_rand_reset.43136859175413810586915671592114672934782211413001643525813995166746276422900
Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_28/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 519488116 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 519493519 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 519493519 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/5
  UVM_INFO @ 519623953 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.59076940636787848037371770892066569228320194145959473115202886000217632506604
Line 111, in log /workspaces/repo/scratch/os_regression_2024_08_28/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2861304816 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2861341404 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2861341404 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 2861701404 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 48 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 41.pattgen_inactive_level.36260162636495556071390179656161037499133715346642983117717366257978246845200
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_08_28/pattgen-sim-xcelium/41.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10004090604 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x507a1550, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10004090604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```