PATTGEN Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	48.000s	66.927us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	53.000s	12.934us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.017m	15.576us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	23.000s	151.372us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	23.000s	122.788us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	56.000s	24.075us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.017m	15.576us	20	20	100.00
		pattgen_csr_aliasing	23.000s	122.788us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.450m	2.657ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	1.900m	5.263ms	50	50	100.00
V2	error	pattgen_error	51.000s	32.537us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.417m	36.768ms	50	50	100.00
V2	alert_test	pattgen_alert_test	1.017m	13.200us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.317m	34.057us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	59.000s	26.493us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	59.000s	26.493us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	53.000s	12.934us	5	5	100.00
		pattgen_csr_rw	1.017m	15.576us	20	20	100.00
		pattgen_csr_aliasing	23.000s	122.788us	5	5	100.00
		pattgen_same_csr_outstanding	1.000m	30.944us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	53.000s	12.934us	5	5	100.00
		pattgen_csr_rw	1.017m	15.576us	20	20	100.00
		pattgen_csr_aliasing	23.000s	122.788us	5	5	100.00
		pattgen_same_csr_outstanding	1.000m	30.944us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.117m	78.028us	20	20	100.00
		pattgen_sec_cm	3.000s	63.803us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.117m	78.028us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.817m	21.428ms	7	50	14.00
V3		TOTAL			7	50	14.00
	Unmapped tests	pattgen_inactive_level	5.067m	10.022ms	44	50	88.00
		TOTAL			521	570	91.40

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 42 failures:

Test pattgen_stress_all_with_rand_reset has 42 failures.

0.pattgen_stress_all_with_rand_reset.14762341415549310674392970050175569085543497467057606564027075675710543672287
Line 153, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1890244937 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1890284004 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1890284004 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 1890367338 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.36253467464152359879992069527292148325523240577759715425246364647720976439125
Line 279, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8312906036 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 8312913236 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 8312913236 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/5
  UVM_INFO @ 8312996570 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 40 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 8.pattgen_inactive_level.19120967847648147193842839423701587890041974977420463987619021439080840458202
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/8.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10110818613 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x3d746dd0, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10110818613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.pattgen_inactive_level.69814473522913479756195488400027852147658999207320111948849869486124931139248
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/24.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10061496715 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb8e45550, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10061496715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 9.pattgen_inactive_level.1466646797828595586700261391970003055888830026364832021013442257126475967711
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/9.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10021999927 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xa2a14ed0, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10021999927 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 11.pattgen_inactive_level.67584677244534625016582564155406959174385443963761879195597732561570904960026
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/11.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10013984197 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xb07f9d50, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10013984197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 14.pattgen_inactive_level.28489297214891274695999747505607414261171015957585242852867916714866980887407
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/14.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10012338419 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x19e8abd0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10012338419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 1 failures:
- Test pattgen_stress_all_with_rand_reset has 1 failures.
  - 43.pattgen_stress_all_with_rand_reset.44305124918239678986695077831357198499908859830721571660462383319832299738071
    Line 116, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/43.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 185792560 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=30) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 47.pattgen_inactive_level.83173280608034773984287096102882680796616937247876459530871323381157444985801
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_08_31/pattgen-sim-xcelium/47.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10009583753 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x3781abd0, Comparison=CompareOpEq, exp_data=0x0, call_count=30)
  UVM_INFO @ 10009583753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```