PATTGEN Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	8.000s	893.525us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	4.000s	26.899us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	3.000s	235.018us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	7.000s	293.622us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	4.000s	49.975us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	4.000s	43.991us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	3.000s	235.018us	20	20	100.00
		pattgen_csr_aliasing	4.000s	49.975us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.100m	2.795ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.400m	4.871ms	50	50	100.00
V2	error	pattgen_error	4.000s	42.956us	50	50	100.00
V2	stress_all	pattgen_stress_all	2.667m	3.983ms	50	50	100.00
V2	alert_test	pattgen_alert_test	4.000s	89.624us	50	50	100.00
V2	intr_test	pattgen_intr_test	4.000s	16.211us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	7.000s	355.223us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	7.000s	355.223us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	4.000s	26.899us	5	5	100.00
		pattgen_csr_rw	3.000s	235.018us	20	20	100.00
		pattgen_csr_aliasing	4.000s	49.975us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	15.114us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	4.000s	26.899us	5	5	100.00
		pattgen_csr_rw	3.000s	235.018us	20	20	100.00
		pattgen_csr_aliasing	4.000s	49.975us	5	5	100.00
		pattgen_same_csr_outstanding	4.000s	15.114us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	4.000s	135.775us	20	20	100.00
		pattgen_sec_cm	4.000s	32.119us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	4.000s	135.775us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.650m	8.334ms	5	50	10.00
V3		TOTAL			5	50	10.00
	Unmapped tests	pattgen_inactive_level	5.883m	10.001ms	47	50	94.00
		TOTAL			522	570	91.58

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 43 failures:

Test pattgen_stress_all_with_rand_reset has 43 failures.

0.pattgen_stress_all_with_rand_reset.30841334049975233008455140024421875636336448088929083311883560818268183345549
Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 327049144 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 327063185 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 327063185 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/10
  UVM_INFO @ 327123185 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.94074239753868472418332115049568511767783024990913208384406099081473003497673
Line 243, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1942847597 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 1942848794 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1942848794 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 1942888794 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 41 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 2 failures:
- Test pattgen_stress_all_with_rand_reset has 2 failures.
  - 3.pattgen_stress_all_with_rand_reset.30432349221344355155761112858678854084445705072002338174223789740997194669490
    Line 162, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/3.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1258126023 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 23.pattgen_stress_all_with_rand_reset.97602232709564327855751315220738719779123277411098582742899692830200091154045
    Line 366, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/23.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3068695510 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 26.pattgen_inactive_level.6451579010794532047521942870279255594756929034976512904706338782118551036274
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/26.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10003323225 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf16e67d0, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10003323225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 28.pattgen_inactive_level.44863743002641880895227597882291808637521450400675052801752903725634668099754
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10001431277 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xca910790, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10001431277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=5) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 37.pattgen_inactive_level.25592166883434811675020566760876639252823779654683140494756446197915496364134
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_03/pattgen-sim-xcelium/37.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10010444737 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x23050610, Comparison=CompareOpEq, exp_data=0x0, call_count=5)
  UVM_INFO @ 10010444737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```