PATTGEN Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	51.000s	423.057us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	14.000s	43.231us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.867m	13.157us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	1.333m	744.826us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	49.000s	47.919us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.367m	87.973us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.867m	13.157us	20	20	100.00
		pattgen_csr_aliasing	49.000s	47.919us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	1.950m	2.834ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.133m	5.164ms	50	50	100.00
V2	error	pattgen_error	42.000s	53.700us	50	50	100.00
V2	stress_all	pattgen_stress_all	4.267m	10.690ms	50	50	100.00
V2	alert_test	pattgen_alert_test	46.000s	57.317us	50	50	100.00
V2	intr_test	pattgen_intr_test	1.233m	42.762us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.383m	43.936us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.383m	43.936us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	14.000s	43.231us	5	5	100.00
		pattgen_csr_rw	1.867m	13.157us	20	20	100.00
		pattgen_csr_aliasing	49.000s	47.919us	5	5	100.00
		pattgen_same_csr_outstanding	2.500m	15.255us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	14.000s	43.231us	5	5	100.00
		pattgen_csr_rw	1.867m	13.157us	20	20	100.00
		pattgen_csr_aliasing	49.000s	47.919us	5	5	100.00
		pattgen_same_csr_outstanding	2.500m	15.255us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	1.483m	137.756us	20	20	100.00
		pattgen_sec_cm	4.000s	63.682us	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.483m	137.756us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.533m	19.502ms	4	50	8.00
V3		TOTAL			4	50	8.00
	Unmapped tests	pattgen_inactive_level	2.600m	10.316ms	43	50	86.00
		TOTAL			517	570	90.70

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 46 failures:

Test pattgen_stress_all_with_rand_reset has 46 failures.

0.pattgen_stress_all_with_rand_reset.108595438419986859219579769230599609188843615950732932776554297449312444796603
Line 151, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6789117463 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 6789160358 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 6789160358 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 2/10
  UVM_INFO @ 6789410358 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

1.pattgen_stress_all_with_rand_reset.103722264327312403348472651763659154697255394465709622038857430008724610151774
Line 234, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2985208824 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 2985220887 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 2985220887 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 4/10
  UVM_INFO @ 2985286104 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 44 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 2 failures:
- Test pattgen_inactive_level has 2 failures.
  - 34.pattgen_inactive_level.38814893523981636348539800000956414261126885113850661693537403233416280403714
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/34.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10024657192 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xf666f650, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10024657192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.pattgen_inactive_level.85139055272428536230466840076548778611044867196635479418780669228981535874386
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/49.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10315956529 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x415e3f50, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10315956529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 25.pattgen_inactive_level.6009279405378882019388188222100606962757207450487434860135762920989313729665
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/25.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016690204 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x45a1e390, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10016690204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=22) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 33.pattgen_inactive_level.84039460526887795145305965467160213240439702144086390751321204600402281925338
    Line 91, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/33.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10042164304 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0xcc2e8e50, Comparison=CompareOpEq, exp_data=0x0, call_count=22)
  UVM_INFO @ 10042164304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=9) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 35.pattgen_inactive_level.46421751846420259826934811573055708956446387850364192706427781678475306400849
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/35.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10132317978 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xca958d90, Comparison=CompareOpEq, exp_data=0x0, call_count=9)
  UVM_INFO @ 10132317978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 36.pattgen_inactive_level.108112571637779810971583981167413421160157228458769465966173934318978533988009
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10032173044 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch1 (addr=0x68475dd0, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10032173044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=19) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 46.pattgen_inactive_level.40744231541142491938677193334103003978021616690396152673444384195103300274365
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_08/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10054962651 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xda377210, Comparison=CompareOpEq, exp_data=0x0, call_count=19)
  UVM_INFO @ 10054962651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```