PATTGEN Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: XCELIUM

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	42.000s	64.065us	50	50	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.633m	14.475us	5	5	100.00
V1	csr_rw	pattgen_csr_rw	1.617m	32.063us	20	20	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.250m	364.671us	5	5	100.00
V1	csr_aliasing	pattgen_csr_aliasing	2.117m	27.555us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	2.933m	27.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.617m	32.063us	20	20	100.00
		pattgen_csr_aliasing	2.117m	27.555us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	perf	pattgen_perf	2.617m	4.816ms	50	50	100.00
V2	cnt_rollover	cnt_rollover	2.033m	7.797ms	50	50	100.00
V2	error	pattgen_error	47.000s	16.566us	50	50	100.00
V2	stress_all	pattgen_stress_all	1.900m	31.930ms	50	50	100.00
V2	alert_test	pattgen_alert_test	48.000s	51.091us	50	50	100.00
V2	intr_test	pattgen_intr_test	3.050m	21.800us	50	50	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	1.617m	749.542us	20	20	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	1.617m	749.542us	20	20	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.633m	14.475us	5	5	100.00
		pattgen_csr_rw	1.617m	32.063us	20	20	100.00
		pattgen_csr_aliasing	2.117m	27.555us	5	5	100.00
		pattgen_same_csr_outstanding	2.817m	40.897us	20	20	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.633m	14.475us	5	5	100.00
		pattgen_csr_rw	1.617m	32.063us	20	20	100.00
		pattgen_csr_aliasing	2.117m	27.555us	5	5	100.00
		pattgen_same_csr_outstanding	2.817m	40.897us	20	20	100.00
V2		TOTAL			340	340	100.00
V2S	tl_intg_err	pattgen_tl_intg_err	3.050m	42.394us	20	20	100.00
		pattgen_sec_cm	4.000s	1.078ms	5	5	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	3.050m	42.394us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	3.417m	9.653ms	1	50	2.00
V3		TOTAL			1	50	2.00
	Unmapped tests	pattgen_inactive_level	4.683m	10.045ms	45	50	90.00
		TOTAL			516	570	90.53

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	0	0.00
V1	6	6	6	100.00
V2	8	8	8	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.88	100.00	100.00	100.00	99.16	96.13	--	100.00	89.95

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:868) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 45 failures:

Test pattgen_stress_all_with_rand_reset has 45 failures.

1.pattgen_stress_all_with_rand_reset.41043219288728237462280522006248076543332017133153836622170627830586899412533
Line 258, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/1.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20315698597 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 20315896018 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 20315896018 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 5/10
  UVM_INFO @ 20316296018 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

2.pattgen_stress_all_with_rand_reset.70638510750968549312073754815121472930000785290962645855361285696456336929485
Line 103, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/2.pattgen_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 241029765 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_ERROR @ 241051025 ps: (cip_base_vseq.sv:772) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 241051025 ps: (cip_base_vseq.sv:775) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
  Issuing reset for run 1/5
  UVM_INFO @ 241265315 ps: (cip_base_vseq.sv:796) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]

... and 43 more failures.

UVM_ERROR (pattgen_scoreboard.sv:207) scoreboard [scoreboard] has 4 failures:
- Test pattgen_stress_all_with_rand_reset has 4 failures.
  - 4.pattgen_stress_all_with_rand_reset.102079018822401302034619558737537046395412912495099264026675167343705671798937
    Line 116, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/4.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 235941395 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 0 item mismatch!
  --> EXP:
  ------------------------------------
  Name      Type          Size  Value
```
  - 6.pattgen_stress_all_with_rand_reset.73493566118649311492336530740490020961137726949796744755446564310258559109890
    Line 153, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/6.pattgen_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 248351648 ps: (pattgen_scoreboard.sv:207) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
  --> channel 1 item mismatch!
  --> EXP:
  -------------------------------------
  Name       Type          Size  Value
```
  - ... and 2 more failures.
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 1.pattgen_inactive_level.108462820579122369763173176279043063503942700267939136486712612461830638020245
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/1.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10016066566 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x6684ed50, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10016066566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 6.pattgen_inactive_level.27141293013359231997760957589387335117086294116510364750680745944058891077594
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/6.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10120301668 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xb894b10, Comparison=CompareOpEq, exp_data=0x0, call_count=13)
  UVM_INFO @ 10120301668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=29) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 28.pattgen_inactive_level.98814172711394163136446273950116405601722017192556262990417649392897068784758
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/28.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10045095009 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x841850, Comparison=CompareOpEq, exp_data=0x0, call_count=29)
  UVM_INFO @ 10045095009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=15) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 36.pattgen_inactive_level.14265727689517233457506428625786474632067939479430730832325788238041783078427
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/36.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10028886317 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0xcefa8c90, Comparison=CompareOpEq, exp_data=0x0, call_count=15)
  UVM_INFO @ 10028886317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch* (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3) has 1 failures:
- Test pattgen_inactive_level has 1 failures.
  - 46.pattgen_inactive_level.39742467498469527976740337892727842711451593094719423328113025930973974077575
    Line 89, in log /workspaces/repo/scratch/os_regression_2024_09_10/pattgen-sim-xcelium/46.pattgen_inactive_level/latest/run.log
```
  UVM_FATAL @ 10008663430 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout pattgen_reg_block.ctrl.enable_ch0 (addr=0x2d8f33d0, Comparison=CompareOpEq, exp_data=0x0, call_count=3)
  UVM_INFO @ 10008663430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```