042415198f
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 9.000s | 1.459ms | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 59.961us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 12.000s | 14.661us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 837.915us | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 153.152us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 7.000s | 19.207us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 12.000s | 14.661us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 3.000s | 153.152us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | pulse | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | blink | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | heartbeat | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | resolution | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | multi_channel | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | polarity | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | phase | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | lowpower | pwm_rand_output | 1.233m | 10.505ms | 50 | 50 | 100.00 |
V2 | perf | pwm_perf | 50.000s | 10.941ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.617m | 54.613ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 8.000s | 19.533us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 7.000s | 13.555us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 9.000s | 92.578us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 9.000s | 92.578us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 59.961us | 5 | 5 | 100.00 |
pwm_csr_rw | 12.000s | 14.661us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 153.152us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 8.000s | 133.143us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 59.961us | 5 | 5 | 100.00 |
pwm_csr_rw | 12.000s | 14.661us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 3.000s | 153.152us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 8.000s | 133.143us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 287 | 290 | 98.97 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 9.000s | 92.910us | 20 | 20 | 100.00 |
pwm_sec_cm | 2.000s | 117.730us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 9.000s | 92.910us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 417 | 420 | 99.29 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 6 | 85.71 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.39 | 99.34 | 98.83 | 99.84 | 94.86 | 94.92 | -- | 100.00 | 99.34 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 3 failures:
35.pwm_stress_all.112718364360976177288589792118373076540358536539584646706420943197635306541829
Line 577, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/35.pwm_stress_all/latest/run.log
UVM_ERROR @ 44480524894 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 44480524894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
39.pwm_stress_all.115727987894470213234978051821050384915205503332246554126570617853906053990619
Line 115982, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/39.pwm_stress_all/latest/run.log
UVM_ERROR @ 533175904312 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 533175904312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.