PWM Simulation Results

Wednesday January 31 2024 20:02:52 UTC

GitHub Revision: 4ddd81322f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 21932966400645871531253577545734825173576945735198195365995401811578215479543

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 0 50 0.00
V1 csr_hw_reset pwm_csr_hw_reset 0 5 0.00
V1 csr_rw pwm_csr_rw 0 20 0.00
V1 csr_bit_bash pwm_csr_bit_bash 0 5 0.00
V1 csr_aliasing pwm_csr_aliasing 0 5 0.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 0 20 0.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 0 20 0.00
pwm_csr_aliasing 0 5 0.00
V1 TOTAL 0 105 0.00
V2 dutycycle pwm_rand_output 0 50 0.00
V2 pulse pwm_rand_output 0 50 0.00
V2 blink pwm_rand_output 0 50 0.00
V2 heartbeat pwm_rand_output 0 50 0.00
V2 resolution pwm_rand_output 0 50 0.00
V2 multi_channel pwm_rand_output 0 50 0.00
V2 polarity pwm_rand_output 0 50 0.00
V2 phase pwm_rand_output 0 50 0.00
V2 lowpower pwm_rand_output 0 50 0.00
V2 perf pwm_perf 0 50 0.00
V2 stress_all pwm_stress_all 0 50 0.00
V2 alert_test pwm_alert_test 0 50 0.00
V2 intr_test pwm_intr_test 0 50 0.00
V2 tl_d_oob_addr_access pwm_tl_errors 0 20 0.00
V2 tl_d_illegal_access pwm_tl_errors 0 20 0.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 0 5 0.00
pwm_csr_rw 0 20 0.00
pwm_csr_aliasing 0 5 0.00
pwm_same_csr_outstanding 0 20 0.00
V2 tl_d_partial_access pwm_csr_hw_reset 0 5 0.00
pwm_csr_rw 0 20 0.00
pwm_csr_aliasing 0 5 0.00
pwm_same_csr_outstanding 0 20 0.00
V2 TOTAL 0 290 0.00
V2S tl_intg_err pwm_tl_intg_err 0 20 0.00
pwm_sec_cm 0 5 0.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 0 20 0.00
V2S TOTAL 0 25 0.00
V3 TOTAL 0 0 --
TOTAL 0 420 0.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 0 0.00
V2 7 7 0 0.00
V2S 2 2 0 0.00

Failure Buckets

Past Results