PWM Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	1.412ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	35.295us	5	5	100.00
V1	csr_rw	pwm_csr_rw	6.000s	185.487us	19	20	95.00
V1	csr_bit_bash	pwm_csr_bit_bash	13.000s	2.362ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	268.204us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	6.000s	68.511us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	6.000s	185.487us	19	20	95.00
		pwm_csr_aliasing	5.000s	268.204us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	dutycycle	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	pulse	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	blink	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	resolution	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	polarity	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	phase	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.333m	21.006ms	50	50	100.00
V2	perf	pwm_perf	52.000s	10.720ms	49	50	98.00
V2	stress_all	pwm_stress_all	7.950m	105.998ms	50	50	100.00
V2	alert_test	pwm_alert_test	3.000s	13.058us	50	50	100.00
V2	intr_test	pwm_intr_test	9.000s	14.712us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	10.000s	53.968us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	10.000s	53.968us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	35.295us	5	5	100.00
		pwm_csr_rw	6.000s	185.487us	19	20	95.00
		pwm_csr_aliasing	5.000s	268.204us	5	5	100.00
		pwm_same_csr_outstanding	7.000s	37.000us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	35.295us	5	5	100.00
		pwm_csr_rw	6.000s	185.487us	19	20	95.00
		pwm_csr_aliasing	5.000s	268.204us	5	5	100.00
		pwm_same_csr_outstanding	7.000s	37.000us	20	20	100.00
V2		TOTAL			289	290	99.66
V2S	tl_intg_err	pwm_tl_intg_err	6.000s	185.143us	20	20	100.00
		pwm_sec_cm	4.000s	41.430us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	6.000s	185.143us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.46	99.48	99.08	99.92	94.79	94.92	--	100.00	99.34

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:

  • Test pwm_perf has 1 failures.

    • 13.pwm_perf.79593268430057082299053536102092009296360346066023930524303875862088338483735
      Line 329, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/13.pwm_perf/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job pwm-sim-xcelium_run_cover_reg_top killed due to: Exit reason: Error: * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *] has 1 failures:

  • Test pwm_csr_rw has 1 failures.

    • 15.pwm_csr_rw.95699469283842767072054042935401156000384209303140314399085915171018687627949
      Log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/15.pwm_csr_rw/latest/run.log

        Job ID: smart:aeff9a60-253f-4150-88a0-b8aa1177828f
      

Past Results

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• 2024.01.22_11.04.36
• 2024.01.18_08.44.23
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