PWM Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: `bc285b7382`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	20.000s	2.041ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	7.000s	62.681us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	14.027us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	547.815us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	120.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	197.513us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	14.027us	20	20	100.00
		pwm_csr_aliasing	4.000s	120.811us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	pulse	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	blink	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	heartbeat	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	resolution	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	multi_channel	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	polarity	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	phase	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	lowpower	pwm_rand_output	1.250m	12.216ms	50	50	100.00
V2	perf	pwm_perf	58.000s	43.746ms	49	50	98.00
V2	stress_all	pwm_stress_all	5.167m	334.035ms	48	50	96.00
V2	alert_test	pwm_alert_test	16.000s	59.826us	50	50	100.00
V2	intr_test	pwm_intr_test	8.000s	12.533us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	9.000s	65.496us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	9.000s	65.496us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	7.000s	62.681us	5	5	100.00
		pwm_csr_rw	3.000s	14.027us	20	20	100.00
		pwm_csr_aliasing	4.000s	120.811us	5	5	100.00
		pwm_same_csr_outstanding	7.000s	24.282us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	7.000s	62.681us	5	5	100.00
		pwm_csr_rw	3.000s	14.027us	20	20	100.00
		pwm_csr_aliasing	4.000s	120.811us	5	5	100.00
		pwm_same_csr_outstanding	7.000s	24.282us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	8.000s	60.895us	20	20	100.00
		pwm_sec_cm	8.000s	320.743us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	8.000s	60.895us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.08	99.03	98.28	99.76	94.21	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

2.pwm_stress_all.28616958189328834530469058222251872802445545357845112753151833997260758166036
Line 23368, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/2.pwm_stress_all/latest/run.log

  UVM_ERROR @ 21359433427 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 21359433427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.pwm_stress_all.76967468535438105245657593288672219124127975186842799608944238089800781948423
Line 67228, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/45.pwm_stress_all/latest/run.log

  UVM_ERROR @ 43624175206 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 43624175206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 25.pwm_perf.925731794798040302572316564900217541875390728292645083251278063672172913989
    Line 329, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/25.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```