PWM Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: `e844018f2c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	15.000s	1.411ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	4.000s	23.738us	5	5	100.00
V1	csr_rw	pwm_csr_rw	5.000s	16.953us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	12.000s	166.086us	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	5.000s	62.978us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	5.000s	56.305us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	5.000s	16.953us	20	20	100.00
		pwm_csr_aliasing	5.000s	62.978us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	pulse	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	blink	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	resolution	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	polarity	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	phase	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.467m	10.504ms	50	50	100.00
V2	perf	pwm_perf	55.000s	10.506ms	49	50	98.00
V2	stress_all	pwm_stress_all	4.033m	244.226ms	48	50	96.00
V2	alert_test	pwm_alert_test	12.000s	21.734us	50	50	100.00
V2	intr_test	pwm_intr_test	12.000s	36.160us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	10.000s	406.322us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	10.000s	406.322us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	4.000s	23.738us	5	5	100.00
		pwm_csr_rw	5.000s	16.953us	20	20	100.00
		pwm_csr_aliasing	5.000s	62.978us	5	5	100.00
		pwm_same_csr_outstanding	14.000s	38.102us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	4.000s	23.738us	5	5	100.00
		pwm_csr_rw	5.000s	16.953us	20	20	100.00
		pwm_csr_aliasing	5.000s	62.978us	5	5	100.00
		pwm_same_csr_outstanding	14.000s	38.102us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	8.000s	272.394us	20	20	100.00
		pwm_sec_cm	13.000s	42.684us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	8.000s	272.394us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.60	99.59	99.26	99.96	95.20	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

20.pwm_stress_all.6393387752250209406260751229816218852706088368073605472649573062416038082266
Line 602, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/20.pwm_stress_all/latest/run.log

  UVM_ERROR @ 43764070534 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 43764070534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.pwm_stress_all.49618868999490310755613842530779646105697335888867259790305963332168100002294
Line 661, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_stress_all/latest/run.log

  UVM_ERROR @ 42858789966 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 42858789966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_perf has 1 failures.
  - 23.pwm_perf.95232716840529028310773618104924743929593162484564971982983473174794962770865
    Line 379, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```