c187a82ee8
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | pwm_smoke | 6.000s | 513.244us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | pwm_csr_hw_reset | 4.000s | 51.762us | 5 | 5 | 100.00 |
V1 | csr_rw | pwm_csr_rw | 4.000s | 68.556us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | pwm_csr_bit_bash | 12.000s | 7.707ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | pwm_csr_aliasing | 6.000s | 373.904us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 5.000s | 58.333us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 4.000s | 68.556us | 20 | 20 | 100.00 |
pwm_csr_aliasing | 6.000s | 373.904us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 105 | 105 | 100.00 | |||
V2 | dutycycle | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | pulse | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | blink | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | heartbeat | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | resolution | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | multi_channel | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | polarity | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | phase | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | lowpower | pwm_rand_output | 2.117m | 21.004ms | 49 | 50 | 98.00 |
V2 | perf | pwm_perf | 50.000s | 11.669ms | 50 | 50 | 100.00 |
V2 | stress_all | pwm_stress_all | 4.917m | 190.920ms | 47 | 50 | 94.00 |
V2 | alert_test | pwm_alert_test | 4.000s | 16.024us | 50 | 50 | 100.00 |
V2 | intr_test | pwm_intr_test | 4.000s | 50.278us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | pwm_tl_errors | 9.000s | 179.373us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | pwm_tl_errors | 9.000s | 179.373us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 4.000s | 51.762us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 68.556us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 6.000s | 373.904us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 5.000s | 129.211us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | pwm_csr_hw_reset | 4.000s | 51.762us | 5 | 5 | 100.00 |
pwm_csr_rw | 4.000s | 68.556us | 20 | 20 | 100.00 | ||
pwm_csr_aliasing | 6.000s | 373.904us | 5 | 5 | 100.00 | ||
pwm_same_csr_outstanding | 5.000s | 129.211us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 286 | 290 | 98.62 | |||
V2S | tl_intg_err | pwm_tl_intg_err | 6.000s | 132.020us | 20 | 20 | 100.00 |
pwm_sec_cm | 3.000s | 82.769us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 6.000s | 132.020us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 416 | 420 | 99.05 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 6 | 6 | 6 | 100.00 |
V2 | 7 | 7 | 5 | 71.43 |
V2S | 2 | 2 | 2 | 100.00 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
98.56 | 99.55 | 99.20 | 99.92 | 95.13 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard]
has 4 failures:
1.pwm_stress_all.7371288404952877006431466418910539282570811639912631955037760548084955944736
Line 86598, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/1.pwm_stress_all/latest/run.log
UVM_ERROR @ 43815383563 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 43815383563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.pwm_stress_all.50183326033690360098159333410912175545059950696582967018370494136714932549251
Line 16931, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/18.pwm_stress_all/latest/run.log
UVM_ERROR @ 18631311669 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 18631311669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
30.pwm_rand_output.102847713661550597386413775162228856949661969950803745321755441999721731851912
Line 403, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/30.pwm_rand_output/latest/run.log
UVM_ERROR @ 4819785572 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [4] did not MATCH
UVM_INFO @ 4819785572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---