919341eb22| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 5.000s | 4.235ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 2.000s | 33.731us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 5.000s | 21.493us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 19.000s | 675.961us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 9.000s | 69.954us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 10.000s | 45.903us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 5.000s | 21.493us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 9.000s | 69.954us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | pulse | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | blink | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | heartbeat | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | resolution | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | multi_channel | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | polarity | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | phase | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | lowpower | pwm_rand_output | 1.517m | 10.830ms | 48 | 50 | 96.00 |
| V2 | perf | pwm_perf | 50.000s | 10.502ms | 50 | 50 | 100.00 |
| V2 | stress_all | pwm_stress_all | 4.700m | 133.421ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 3.000s | 41.139us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 13.325us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 10.000s | 383.427us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 10.000s | 383.427us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 2.000s | 33.731us | 5 | 5 | 100.00 |
| pwm_csr_rw | 5.000s | 21.493us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 9.000s | 69.954us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 95.219us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 2.000s | 33.731us | 5 | 5 | 100.00 |
| pwm_csr_rw | 5.000s | 21.493us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 9.000s | 69.954us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 5.000s | 95.219us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 284 | 290 | 97.93 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 11.000s | 541.318us | 20 | 20 | 100.00 |
| pwm_sec_cm | 2.000s | 228.303us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 11.000s | 541.318us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 414 | 420 | 98.57 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.57 | 99.59 | 99.26 | 99.88 | 95.20 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
7.pwm_stress_all.27304149892773796317438545797245680453975594469412948621168843399685289384876
Line 85042, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/7.pwm_stress_all/latest/run.log
UVM_ERROR @ 53571977379 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 53571977379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.pwm_stress_all.72886396177956036958293663411387218026693384849668228388563102685000983448656
Line 362442, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_stress_all/latest/run.log
UVM_ERROR @ 43453440532 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 43453440532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
7.pwm_rand_output.6582511515055859106386203375332917169806485942754856190331935852942493877836
Line 353, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/7.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.pwm_rand_output.95716443620795576540659536960540406614384074527270277318005287154346576218590
Line 1999774, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/22.pwm_rand_output/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---