PWM Simulation Results

Tuesday April 02 2024 19:02:21 UTC

GitHub Revision: 1fbe1ece8d

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 10515816417091650402163962333134174777740454699264757911298152460288222033634

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 7.000s 2.126ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 5.000s 36.618us 5 5 100.00
V1 csr_rw pwm_csr_rw 6.000s 18.231us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 10.000s 282.792us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 6.000s 91.131us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 7.000s 205.463us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 6.000s 18.231us 20 20 100.00
pwm_csr_aliasing 6.000s 91.131us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 pulse pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 blink pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 heartbeat pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 resolution pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 multi_channel pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 polarity pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 phase pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 lowpower pwm_rand_output 2.233m 21.434ms 49 50 98.00
V2 perf pwm_perf 51.000s 43.744ms 50 50 100.00
V2 stress_all pwm_stress_all 5.167m 74.008ms 47 50 94.00
V2 alert_test pwm_alert_test 7.000s 15.301us 50 50 100.00
V2 intr_test pwm_intr_test 7.000s 11.477us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 9.000s 45.696us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 9.000s 45.696us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 5.000s 36.618us 5 5 100.00
pwm_csr_rw 6.000s 18.231us 20 20 100.00
pwm_csr_aliasing 6.000s 91.131us 5 5 100.00
pwm_same_csr_outstanding 7.000s 672.677us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 5.000s 36.618us 5 5 100.00
pwm_csr_rw 6.000s 18.231us 20 20 100.00
pwm_csr_aliasing 6.000s 91.131us 5 5 100.00
pwm_same_csr_outstanding 7.000s 672.677us 20 20 100.00
V2 TOTAL 286 290 98.62
V2S tl_intg_err pwm_tl_intg_err 9.000s 556.607us 20 20 100.00
pwm_sec_cm 3.000s 426.996us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 9.000s 556.607us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 416 420 99.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 5 71.43
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.57 99.52 99.14 100.00 95.13 94.92 -- 100.00 99.01

Failure Buckets

Past Results