PWM Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	1.090ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	16.585us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	40.896us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	1.260ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	925.456us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	111.973us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	40.896us	20	20	100.00
		pwm_csr_aliasing	4.000s	925.456us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	pulse	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	blink	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	resolution	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	polarity	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	phase	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.617m	10.718ms	49	50	98.00
V2	perf	pwm_perf	50.000s	21.879ms	50	50	100.00
V2	stress_all	pwm_stress_all	8.433m	253.981ms	47	50	94.00
V2	alert_test	pwm_alert_test	3.000s	13.634us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	18.299us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	91.860us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	91.860us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	16.585us	5	5	100.00
		pwm_csr_rw	3.000s	40.896us	20	20	100.00
		pwm_csr_aliasing	4.000s	925.456us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	181.920us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	16.585us	5	5	100.00
		pwm_csr_rw	3.000s	40.896us	20	20	100.00
		pwm_csr_aliasing	4.000s	925.456us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	181.920us	20	20	100.00
V2		TOTAL			286	290	98.62
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	514.057us	20	20	100.00
		pwm_sec_cm	3.000s	126.548us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	514.057us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			416	420	99.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.52	99.55	99.20	99.84	95.10	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:

Test pwm_stress_all has 3 failures.

1.pwm_stress_all.63918606010452123748878693532208491808395521786008772749377257279871066871791
Line 651, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/1.pwm_stress_all/latest/run.log

  UVM_ERROR @ 91289151460 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 91289151460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.pwm_stress_all.37647943105886015434465224678751138752286388499930329092568419079356153053887
Line 16938, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11526691689 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 11526691689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_rand_output has 1 failures.
  - 24.pwm_rand_output.55318456700740883951650116759656962812499589225284636124555948681229918973124
    Line 62656, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/24.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```