d0c52cdadd| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 10.000s | 2.215ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 29.973us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 28.211us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 11.000s | 1.299ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 3.000s | 351.202us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 3.000s | 50.099us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 28.211us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 3.000s | 351.202us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 1.083m | 42.005ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 55.000s | 10.828ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 4.800m | 212.046ms | 46 | 50 | 92.00 |
| V2 | alert_test | pwm_alert_test | 14.000s | 32.664us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 3.000s | 14.197us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 6.000s | 564.508us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 6.000s | 564.508us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 29.973us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 28.211us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 351.202us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 322.872us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 29.973us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 28.211us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 3.000s | 351.202us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 3.000s | 322.872us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 285 | 290 | 98.28 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 4.000s | 325.656us | 20 | 20 | 100.00 |
| pwm_sec_cm | 3.000s | 39.110us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 4.000s | 325.656us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 415 | 420 | 98.81 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.49 | 99.48 | 99.08 | 99.76 | 95.24 | 94.92 | -- | 100.00 | 99.01 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 4 failures:
15.pwm_stress_all.34616879471112351048318374046932189738755804134476028834201708405806945027459
Line 903, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/15.pwm_stress_all/latest/run.log
UVM_ERROR @ 33696545595 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 33696545595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.pwm_stress_all.46245074468631937240284432804720366828573920309457387257313519055500473657214
Line 5537, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/20.pwm_stress_all/latest/run.log
UVM_ERROR @ 42425227453 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [2] did not MATCH
UVM_INFO @ 42425227453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
22.pwm_perf.27802546926709680017804936333385655632930970435746921416500478554173755442380
Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/22.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---