PWM Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	1.025ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	3.000s	88.391us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	19.739us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	1.590ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	82.756us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	62.473us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	19.739us	20	20	100.00
		pwm_csr_aliasing	4.000s	82.756us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	pulse	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	blink	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	resolution	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	polarity	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	phase	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.733m	10.506ms	49	50	98.00
V2	perf	pwm_perf	50.000s	10.716ms	48	50	96.00
V2	stress_all	pwm_stress_all	7.850m	87.629ms	48	50	96.00
V2	alert_test	pwm_alert_test	4.000s	36.411us	50	50	100.00
V2	intr_test	pwm_intr_test	4.000s	12.623us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	7.000s	441.499us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	7.000s	441.499us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	3.000s	88.391us	5	5	100.00
		pwm_csr_rw	3.000s	19.739us	20	20	100.00
		pwm_csr_aliasing	4.000s	82.756us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	36.139us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	3.000s	88.391us	5	5	100.00
		pwm_csr_rw	3.000s	19.739us	20	20	100.00
		pwm_csr_aliasing	4.000s	82.756us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	36.139us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	133.228us	20	20	100.00
		pwm_sec_cm	3.000s	67.532us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	133.228us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.45	99.45	99.01	99.88	94.89	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:

Test pwm_rand_output has 1 failures.

6.pwm_rand_output.14982022226332037625806096321050427557979711179425260439369981188569652751304
Line 352, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/6.pwm_rand_output/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwm_perf has 2 failures.

26.pwm_perf.37196534824689564497375856019040591276458784693079689839765488472437324731318
Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/26.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

31.pwm_perf.42095308933776371101261529289257198245527295283985849192389018070089083331948
Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/31.pwm_perf/latest/run.log

  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

15.pwm_stress_all.64327922586344204704200852343311936481679945849634234370843418242031344096870
Line 787220, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/15.pwm_stress_all/latest/run.log

  UVM_ERROR @ 63701085570 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 63701085570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.pwm_stress_all.31763146059313532840224161256104403952650290502614854652003389549537872494645
Line 7060925, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/41.pwm_stress_all/latest/run.log

  UVM_ERROR @ 33181144857 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 33181144857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---