PWM Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	2.204ms	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	17.983us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	68.149us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	2.446ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	138.015us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	4.000s	53.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	68.149us	20	20	100.00
		pwm_csr_aliasing	4.000s	138.015us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	pulse	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	blink	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	heartbeat	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	resolution	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	multi_channel	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	polarity	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	phase	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	lowpower	pwm_rand_output	4.217m	20.199ms	50	50	100.00
V2	perf	pwm_perf	52.000s	40.379ms	47	50	94.00
V2	stress_all	pwm_stress_all	4.417m	73.493ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	44.989us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	21.561us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	117.348us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	117.348us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	17.983us	5	5	100.00
		pwm_csr_rw	3.000s	68.149us	20	20	100.00
		pwm_csr_aliasing	4.000s	138.015us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	38.641us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	17.983us	5	5	100.00
		pwm_csr_rw	3.000s	68.149us	20	20	100.00
		pwm_csr_aliasing	4.000s	138.015us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	38.641us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	141.591us	20	20	100.00
		pwm_sec_cm	3.000s	228.974us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	141.591us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.46	99.48	99.08	99.92	94.83	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test pwm_perf has 3 failures.
  - 3.pwm_perf.13876865458079276071609478977644844650558921754077855291259449569203809691391
    Line 375, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/3.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.pwm_perf.17739830751802514266520718202179781110677912168379991187457452746793437082490
    Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

19.pwm_stress_all.46284953807277444787807048564178175920840227866198483942202411582699137245411
Line 656459, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/19.pwm_stress_all/latest/run.log

  UVM_ERROR @ 22754536713 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [2] did not MATCH
  UVM_INFO @ 22754536713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.pwm_stress_all.93761335477380154578941497954073053319479186245429514442591130696570720240331
Line 130052, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/47.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11441646534 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 11441646534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---