PWM Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	512.373us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	7.000s	19.817us	5	5	100.00
V1	csr_rw	pwm_csr_rw	7.000s	69.269us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	11.000s	4.542ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	9.000s	399.580us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	13.000s	29.805us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	7.000s	69.269us	20	20	100.00
		pwm_csr_aliasing	9.000s	399.580us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	pulse	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	blink	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	heartbeat	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	resolution	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	multi_channel	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	polarity	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	phase	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	lowpower	pwm_rand_output	1.200m	10.831ms	49	50	98.00
V2	perf	pwm_perf	49.000s	12.966ms	50	50	100.00
V2	stress_all	pwm_stress_all	6.950m	54.126ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	15.377us	50	50	100.00
V2	intr_test	pwm_intr_test	8.000s	11.999us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	14.000s	490.833us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	14.000s	490.833us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	7.000s	19.817us	5	5	100.00
		pwm_csr_rw	7.000s	69.269us	20	20	100.00
		pwm_csr_aliasing	9.000s	399.580us	5	5	100.00
		pwm_same_csr_outstanding	8.000s	23.396us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	7.000s	19.817us	5	5	100.00
		pwm_csr_rw	7.000s	69.269us	20	20	100.00
		pwm_csr_aliasing	9.000s	399.580us	5	5	100.00
		pwm_same_csr_outstanding	8.000s	23.396us	20	20	100.00
V2		TOTAL			287	290	98.97
V2S	tl_intg_err	pwm_tl_intg_err	13.000s	153.278us	20	20	100.00
		pwm_sec_cm	3.000s	66.865us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	13.000s	153.278us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			417	420	99.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	5	71.43
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.53	99.59	99.26	99.92	94.93	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

0.pwm_stress_all.67207761518932310486418231748935812792563322197989716799040542901770179719322
Line 483, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/0.pwm_stress_all/latest/run.log

  UVM_ERROR @ 15963914904 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [1] did not MATCH
  UVM_INFO @ 15963914904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.pwm_stress_all.53999726166255887628795904335460318183358883619896841373707882875725028943341
Line 1813, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/34.pwm_stress_all/latest/run.log

  UVM_ERROR @ 47529687775 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 47529687775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test pwm_rand_output has 1 failures.
  - 5.pwm_rand_output.191772016732843471562127462681398217773446362854964702049580337126779725847
    Line 404, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```