PWM Simulation Results

Thursday July 11 2024 23:02:31 UTC

GitHub Revision: edf2fd5092

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110991919330983905489672005724934609038320729526710604109871030362225161447318

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 10.000s 2.203ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 2.000s 75.151us 5 5 100.00
V1 csr_rw pwm_csr_rw 9.000s 36.744us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 9.000s 335.707us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 5.000s 36.219us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 9.000s 34.424us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 9.000s 36.744us 20 20 100.00
pwm_csr_aliasing 5.000s 36.219us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 pulse pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 blink pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 resolution pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 polarity pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 phase pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 lowpower pwm_rand_output 1.900m 40.387ms 50 50 100.00
V2 perf pwm_perf 52.000s 10.505ms 50 50 100.00
V2 stress_all pwm_stress_all 5.233m 147.998ms 50 50 100.00
V2 alert_test pwm_alert_test 7.000s 44.492us 50 50 100.00
V2 intr_test pwm_intr_test 10.000s 13.767us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 8.000s 24.658us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 8.000s 24.658us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 2.000s 75.151us 5 5 100.00
pwm_csr_rw 9.000s 36.744us 20 20 100.00
pwm_csr_aliasing 5.000s 36.219us 5 5 100.00
pwm_same_csr_outstanding 4.000s 24.066us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 2.000s 75.151us 5 5 100.00
pwm_csr_rw 9.000s 36.744us 20 20 100.00
pwm_csr_aliasing 5.000s 36.219us 5 5 100.00
pwm_same_csr_outstanding 4.000s 24.066us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err pwm_tl_intg_err 8.000s 329.934us 20 20 100.00
pwm_sec_cm 7.000s 309.585us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 8.000s 329.934us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 420 420 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.59 99.59 99.26 100.00 95.07 94.92 -- 100.00 99.01

Past Results