c04cc5d074| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwm_smoke | 11.000s | 2.113ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwm_csr_hw_reset | 3.000s | 14.109us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwm_csr_rw | 3.000s | 82.386us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwm_csr_bit_bash | 10.000s | 702.517us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwm_csr_aliasing | 4.000s | 83.706us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwm_csr_mem_rw_with_rand_reset | 8.000s | 36.939us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwm_csr_rw | 3.000s | 82.386us | 20 | 20 | 100.00 |
| pwm_csr_aliasing | 4.000s | 83.706us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | dutycycle | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | pulse | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | blink | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | heartbeat | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | resolution | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | multi_channel | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | polarity | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | phase | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | lowpower | pwm_rand_output | 1.083m | 22.829ms | 50 | 50 | 100.00 |
| V2 | perf | pwm_perf | 53.000s | 10.502ms | 49 | 50 | 98.00 |
| V2 | stress_all | pwm_stress_all | 5.183m | 66.324ms | 47 | 50 | 94.00 |
| V2 | alert_test | pwm_alert_test | 12.000s | 19.583us | 50 | 50 | 100.00 |
| V2 | intr_test | pwm_intr_test | 12.000s | 117.498us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwm_tl_errors | 9.000s | 326.764us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwm_tl_errors | 9.000s | 326.764us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwm_csr_hw_reset | 3.000s | 14.109us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 82.386us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 83.706us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 12.000s | 179.351us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwm_csr_hw_reset | 3.000s | 14.109us | 5 | 5 | 100.00 |
| pwm_csr_rw | 3.000s | 82.386us | 20 | 20 | 100.00 | ||
| pwm_csr_aliasing | 4.000s | 83.706us | 5 | 5 | 100.00 | ||
| pwm_same_csr_outstanding | 12.000s | 179.351us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 286 | 290 | 98.62 | |||
| V2S | tl_intg_err | pwm_tl_intg_err | 8.000s | 184.352us | 20 | 20 | 100.00 |
| pwm_sec_cm | 5.000s | 369.756us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | pwm_tl_intg_err | 8.000s | 184.352us | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| TOTAL | 416 | 420 | 99.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 7 | 7 | 5 | 71.43 |
| V2S | 2 | 2 | 2 | 100.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 98.48 | 99.52 | 99.14 | 99.88 | 94.89 | 94.92 | -- | 100.00 | 99.34 |
UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 3 failures:
10.pwm_stress_all.114772918733974187171592595093878266190860569645387046971772229285810065223996
Line 3212, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/10.pwm_stress_all/latest/run.log
UVM_ERROR @ 79513485758 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [5] did not MATCH
UVM_INFO @ 79513485758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.pwm_stress_all.66727246511928383076043837207121033100714712187889585376836911491044823691718
Line 3554, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_stress_all/latest/run.log
UVM_ERROR @ 317866407442 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [0] did not MATCH
UVM_INFO @ 317866407442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
21.pwm_perf.12937106343623736672131379302590798519081930439131063155136941042177608337840
Line 349, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/21.pwm_perf/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---