PWM Simulation Results

Monday July 15 2024 23:02:37 UTC

GitHub Revision: a04e34f557

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 78455839157994684327892029952813991699715169368132023215715425571513813941951

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 9.000s 1.003ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 2.000s 25.516us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 52.621us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 6.000s 471.455us 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 92.623us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 98.170us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 52.621us 20 20 100.00
pwm_csr_aliasing 4.000s 92.623us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 pulse pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 blink pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 resolution pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 polarity pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 phase pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 lowpower pwm_rand_output 1.033m 10.505ms 50 50 100.00
V2 perf pwm_perf 50.000s 10.503ms 50 50 100.00
V2 stress_all pwm_stress_all 4.283m 109.381ms 50 50 100.00
V2 alert_test pwm_alert_test 7.000s 15.600us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 33.056us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 171.186us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 171.186us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 2.000s 25.516us 5 5 100.00
pwm_csr_rw 3.000s 52.621us 20 20 100.00
pwm_csr_aliasing 4.000s 92.623us 5 5 100.00
pwm_same_csr_outstanding 4.000s 45.005us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 2.000s 25.516us 5 5 100.00
pwm_csr_rw 3.000s 52.621us 20 20 100.00
pwm_csr_aliasing 4.000s 92.623us 5 5 100.00
pwm_same_csr_outstanding 4.000s 45.005us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err pwm_tl_intg_err 5.000s 253.823us 20 20 100.00
pwm_sec_cm 2.000s 59.121us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 253.823us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 420 420 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.57 99.55 99.20 99.80 95.41 94.92 -- 100.00 99.01

Past Results