PWM Simulation Results

Friday July 12 2024 23:02:19 UTC

GitHub Revision: 5967df933a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 46476530947956470787268850137993439884379231200278174763551439909664842175844

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 5.000s 2.536ms 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 3.000s 65.078us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 43.132us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 4.229ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 3.000s 96.378us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 23.958us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 43.132us 20 20 100.00
pwm_csr_aliasing 3.000s 96.378us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 pulse pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 blink pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 heartbeat pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 resolution pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 multi_channel pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 polarity pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 phase pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 lowpower pwm_rand_output 53.000s 10.716ms 50 50 100.00
V2 perf pwm_perf 54.000s 45.644ms 50 50 100.00
V2 stress_all pwm_stress_all 4.583m 66.324ms 50 50 100.00
V2 alert_test pwm_alert_test 3.000s 14.175us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 15.140us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 5.000s 44.683us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 5.000s 44.683us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 3.000s 65.078us 5 5 100.00
pwm_csr_rw 3.000s 43.132us 20 20 100.00
pwm_csr_aliasing 3.000s 96.378us 5 5 100.00
pwm_same_csr_outstanding 4.000s 55.724us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 3.000s 65.078us 5 5 100.00
pwm_csr_rw 3.000s 43.132us 20 20 100.00
pwm_csr_aliasing 3.000s 96.378us 5 5 100.00
pwm_same_csr_outstanding 4.000s 55.724us 20 20 100.00
V2 TOTAL 290 290 100.00
V2S tl_intg_err pwm_tl_intg_err 5.000s 262.453us 20 20 100.00
pwm_sec_cm 3.000s 551.048us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 262.453us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 420 420 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 7 100.00
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.27 99.31 98.77 99.76 94.55 94.92 -- 100.00 99.01

Past Results