PWM Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	5.000s	541.516us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	63.898us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	26.202us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	4.105ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	389.814us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	116.201us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	26.202us	20	20	100.00
		pwm_csr_aliasing	4.000s	389.814us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	pulse	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	blink	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	heartbeat	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	resolution	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	multi_channel	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	polarity	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	phase	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	lowpower	pwm_rand_output	1.850m	20.997ms	48	50	96.00
V2	perf	pwm_perf	51.000s	21.001ms	49	50	98.00
V2	stress_all	pwm_stress_all	3.967m	319.549ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	12.115us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	12.108us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	6.000s	589.030us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	6.000s	589.030us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	63.898us	5	5	100.00
		pwm_csr_rw	3.000s	26.202us	20	20	100.00
		pwm_csr_aliasing	4.000s	389.814us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	205.813us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	63.898us	5	5	100.00
		pwm_csr_rw	3.000s	26.202us	20	20	100.00
		pwm_csr_aliasing	4.000s	389.814us	5	5	100.00
		pwm_same_csr_outstanding	4.000s	205.813us	20	20	100.00
V2		TOTAL			285	290	98.28
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	1.808ms	20	20	100.00
		pwm_sec_cm	3.000s	50.513us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	1.808ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			415	420	98.81

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	4	57.14
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.48	99.52	99.14	99.88	94.93	94.92	--	100.00	99.01

Failure Buckets

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 3 failures:
- Test pwm_rand_output has 2 failures.
  - 23.pwm_rand_output.10025607968596904161749102388121801721347097946318623397735822580843790655715
    Line 143102, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/23.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.pwm_rand_output.90920368151002880552331991389983558561108403873639463437515372217128373873410
    Line 401, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/48.pwm_rand_output/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test pwm_perf has 1 failures.
  - 30.pwm_perf.34540496180488205002190223988697299017040415012227796897339361180747995904858
    Line 399, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/30.pwm_perf/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

25.pwm_stress_all.54643932262805381591245134256917299251755881187712366784658498466193567120338
Line 551, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/25.pwm_stress_all/latest/run.log

  UVM_ERROR @ 11474374813 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 11474374813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.pwm_stress_all.51862855672042791225281431186454443968764416636326732067346188537634246476585
Line 132225, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/49.pwm_stress_all/latest/run.log

  UVM_ERROR @ 656419170563 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [0] did not MATCH
  UVM_INFO @ 656419170563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---