PWM Simulation Results

Saturday July 13 2024 23:02:33 UTC

GitHub Revision: d51405297e

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 101086804359139103922259090811397817605469534164678958852189348539757618502888

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwm_smoke 6.000s 523.869us 50 50 100.00
V1 csr_hw_reset pwm_csr_hw_reset 2.000s 56.215us 5 5 100.00
V1 csr_rw pwm_csr_rw 3.000s 17.487us 20 20 100.00
V1 csr_bit_bash pwm_csr_bit_bash 11.000s 2.842ms 5 5 100.00
V1 csr_aliasing pwm_csr_aliasing 4.000s 312.243us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwm_csr_mem_rw_with_rand_reset 3.000s 95.423us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwm_csr_rw 3.000s 17.487us 20 20 100.00
pwm_csr_aliasing 4.000s 312.243us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 dutycycle pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 pulse pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 blink pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 heartbeat pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 resolution pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 multi_channel pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 polarity pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 phase pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 lowpower pwm_rand_output 1.050m 55.255ms 50 50 100.00
V2 perf pwm_perf 51.000s 21.876ms 50 50 100.00
V2 stress_all pwm_stress_all 4.400m 256.037ms 49 50 98.00
V2 alert_test pwm_alert_test 3.000s 13.884us 50 50 100.00
V2 intr_test pwm_intr_test 3.000s 23.807us 50 50 100.00
V2 tl_d_oob_addr_access pwm_tl_errors 6.000s 156.193us 20 20 100.00
V2 tl_d_illegal_access pwm_tl_errors 6.000s 156.193us 20 20 100.00
V2 tl_d_outstanding_access pwm_csr_hw_reset 2.000s 56.215us 5 5 100.00
pwm_csr_rw 3.000s 17.487us 20 20 100.00
pwm_csr_aliasing 4.000s 312.243us 5 5 100.00
pwm_same_csr_outstanding 3.000s 33.223us 20 20 100.00
V2 tl_d_partial_access pwm_csr_hw_reset 2.000s 56.215us 5 5 100.00
pwm_csr_rw 3.000s 17.487us 20 20 100.00
pwm_csr_aliasing 4.000s 312.243us 5 5 100.00
pwm_same_csr_outstanding 3.000s 33.223us 20 20 100.00
V2 TOTAL 289 290 99.66
V2S tl_intg_err pwm_tl_intg_err 5.000s 95.551us 20 20 100.00
pwm_sec_cm 3.000s 212.867us 5 5 100.00
V2S sec_cm_bus_integrity pwm_tl_intg_err 5.000s 95.551us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 TOTAL 0 0 --
TOTAL 419 420 99.76

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 7 7 6 85.71
V2S 2 2 2 100.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
98.55 99.55 99.20 99.92 95.10 94.92 -- 100.00 99.01

Failure Buckets

Past Results