PWM Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwm_smoke	6.000s	532.963us	50	50	100.00
V1	csr_hw_reset	pwm_csr_hw_reset	2.000s	36.026us	5	5	100.00
V1	csr_rw	pwm_csr_rw	3.000s	70.990us	20	20	100.00
V1	csr_bit_bash	pwm_csr_bit_bash	10.000s	1.289ms	5	5	100.00
V1	csr_aliasing	pwm_csr_aliasing	4.000s	749.575us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwm_csr_mem_rw_with_rand_reset	3.000s	130.704us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwm_csr_rw	3.000s	70.990us	20	20	100.00
		pwm_csr_aliasing	4.000s	749.575us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	dutycycle	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	pulse	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	blink	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	heartbeat	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	resolution	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	multi_channel	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	polarity	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	phase	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	lowpower	pwm_rand_output	2.650m	22.834ms	50	50	100.00
V2	perf	pwm_perf	52.000s	10.945ms	50	50	100.00
V2	stress_all	pwm_stress_all	5.017m	83.981ms	48	50	96.00
V2	alert_test	pwm_alert_test	3.000s	17.201us	50	50	100.00
V2	intr_test	pwm_intr_test	3.000s	45.278us	50	50	100.00
V2	tl_d_oob_addr_access	pwm_tl_errors	5.000s	176.417us	20	20	100.00
V2	tl_d_illegal_access	pwm_tl_errors	5.000s	176.417us	20	20	100.00
V2	tl_d_outstanding_access	pwm_csr_hw_reset	2.000s	36.026us	5	5	100.00
		pwm_csr_rw	3.000s	70.990us	20	20	100.00
		pwm_csr_aliasing	4.000s	749.575us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	22.755us	20	20	100.00
V2	tl_d_partial_access	pwm_csr_hw_reset	2.000s	36.026us	5	5	100.00
		pwm_csr_rw	3.000s	70.990us	20	20	100.00
		pwm_csr_aliasing	4.000s	749.575us	5	5	100.00
		pwm_same_csr_outstanding	3.000s	22.755us	20	20	100.00
V2		TOTAL			288	290	99.31
V2S	tl_intg_err	pwm_tl_intg_err	5.000s	289.764us	20	20	100.00
		pwm_sec_cm	3.000s	297.361us	5	5	100.00
V2S	sec_cm_bus_integrity	pwm_tl_intg_err	5.000s	289.764us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3		TOTAL			0	0	--
		TOTAL			418	420	99.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	7	7	6	85.71
V2S	2	2	2	100.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.65	99.66	99.38	100.00	95.24	94.92	--	100.00	99.01

Failure Buckets

UVM_ERROR (pwm_scoreboard.sv:251) scoreboard [scoreboard] has 2 failures:

Test pwm_stress_all has 2 failures.

5.pwm_stress_all.45704687455669920546623796415012282758647522034856478228926025587712698179380
Line 13664, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/5.pwm_stress_all/latest/run.log

  UVM_ERROR @ 89767082601 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [5] did not MATCH
  UVM_INFO @ 89767082601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.pwm_stress_all.88703083263992199557707621707548556566893059445013693173070800077005876719403
Line 2781, in log /container/opentitan-public/scratch/os_regression/pwm-sim-xcelium/10.pwm_stress_all/latest/run.log

  UVM_ERROR @ 33501580422 ps: (pwm_scoreboard.sv:251) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
   PWM :: Channel = [4] did not MATCH
  UVM_INFO @ 33501580422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---